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Current Path : /usr/lib32/
Current File : //usr/lib32/libpmc.so
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offcore_rsp{"type": "userdata"{"type": "callchain"%s, "pmcid": "0x%08x", "event": "%d", "flags": "0x%08x", "evname": "%s"}
v4GenuineIntel-6-7AAuthenticAMD-23-[[:xdigit:]]+Demand requests that miss L2 cacheumask=0x41,period=200003,event=0x24This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFUl1d_pend_miss.pending_cycles_anyCycles a demand request was blocked due to Fill Buffers inavailabilityRetired store uops that split across a cacheline boundary. (Precise Event - PEBS)  Supports address when precise (Precise event)umask=0x10,period=50021,event=0xd1l2_trans.l2_wbNumber of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of X87 assists due to input valuefp_assist.simd_outputidq.ms_dsb_cyclesUops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyidq_uops_not_delivered.cycles_fe_was_okinv=1,umask=0x1,cmask=1,period=2000003,event=0x9cNumber of times a TSX Abort was triggered due to release/commit but data and address mismatchumask=0x40,period=2000003,event=0xc8rtm_retired.aborted_misc1umask=0x1,period=100007,event=0xcd,ldlat=0x20This event counts loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)cpu_clk_unhalted.thread_anyint_misc.recovery_cyclesThis event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branchesTaken speculative and retired indirect branches with return mnemonicumask=0x84,period=200003,event=0x89uops_executed_port.port_3_coreumask=0x8,any=1,period=2000003,event=0xa1uops_executed_port.port_6cycle_activity.cycles_l2_misscycle_activity.cycles_l1d_pendingNumber of Uops delivered by the LSDumask=0x1,cmask=1,period=2000003,event=0xa8inv=1,umask=0x2,period=2000003,event=0xb1Number of instructions retired. General Counter   - architectural event  Spec update: BDM61inv=1,umask=0x1,cmask=1,period=2000003,event=0xc2umask=0x1,period=400009,event=0xc5umask=0x8,period=100007,event=0xc5LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rspifwdPre-charges due to page misses. Unit: uncore_imc dtlb_load_misses.walk_completed_4kumask=0x10,period=2000003,event=0x8Cycle count for an Extended Page table walkitlb_misses.walk_completed_2m_4mCore misses that miss the  DTLB and hit the STLB (4K)Operations that miss the first ITLB level but hit the second and do not cause any page walksNumber of ITLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98tlb_flush.stlb_anyFrontend_Bound_SMTuops_retired.retire_slots / (4 * cycles)inst_retired.any / cyclesL2_Cache_Fill_BWL2MPKI_Allumask=0x1,period=2000003,cmask=1,event=0x60Counts demand data readsoffcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010002offcore_response.pf_l2_data_rd.supplier_none.snoop_not_neededoffcore_response.pf_l2_data_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020020offcore_response.pf_l2_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0020offcore_response.all_pf_data_rd.supplier_none.snoop_hitmoffcore_response.all_pf_data_rd.l3_hit.snoop_noneoffcore_response.all_pf_data_rd.l3_hit.any_snoopoffcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020091offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwdumask=0x18,period=2000003,cmask=4,event=0x79inv=1,umask=0x1,period=2000003,cmask=1,event=0x9cumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000001offcore_response.corewb.l3_miss_local_dram.snoop_not_neededoffcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000040offcore_response.pf_l2_code_rd.l3_miss.snoop_not_neededoffcore_response.pf_l3_data_rd.l3_hit.snoop_non_dramoffcore_response.pf_l3_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC008000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000090offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dramoffcore_response.all_data_rd.l3_miss.snoop_hit_no_fwdoffcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x3,any=1,period=2000003,cmask=1,event=0xdumask=0x2,period=2000003,cmask=3,event=0xb1unc_cbo_xsnp_response.miss_xcoreumask=0x18,event=0x34unc_cbo_cache_lookup.any_mesiDRAM_Read_LatencyThis event counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event)offcore_response.all_reads.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00002Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cacheConditional branch instructions retired (Precise event)qpi_data_bandwidth_txumask=0x74,period=200000,event=0x29l2_reject_busq.self.any.i_stateumask=0x58,period=200000,event=0x30l2_no_req.selfl1d_cache.all_cache_refSIMD packed shift micro-ops retiredmisalign_mem_ref.ld_splitumask=0x9,period=200000,event=0x5misalign_mem_ref.st_splitprefetch.prefetcht0Number of segment register loadsExternal snoopsumask=0x1,period=2000000,event=0x12cpu_clk_unhalted.core_pbr_inst_retired.pred_takenbr_inst_retired.any1umask=0x3,period=200000,event=0xcLoad uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)offcore_response.any_rfo.l2_miss.anyCounts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600002000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000042000offcore_response.full_streaming_stores.l2_miss.anyCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040010umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000008offcore_response.corewb.l2_miss.hitm_other_coreoffcore_response.demand_rfo.outstandingCounts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this eventCounts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise)Counts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clearmachine_clears.fp_assistbr_inst_retired.jccCounts near indirect CALL branch instructions retired (Must be precise)Counts near relative CALL branch instructions retired (Must be precise)Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise)cycles_div_busy.idivCounts core cycles the integer divide unit is busyCounts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoopsCounts demand cacheable data reads of full cache lines hit the L2 cacheCounts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cacheCounts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the dataPage walk completed due to a demand load to a 4K pagedtlb_load_misses.walk_completed_1gbCounts cycles DSB is delivered four uops. Set Cmask = 4Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled  Spec update: HSD135Randomly selected loads with latency value being above 512  Spec update: HSD76, HSD25, HSM26 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC007F7umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00100Unhalted core cycles when the thread is not in ring 0Cycles which a uop is dispatched on port 5 in this threadCycles with pending L1 cache miss loadsCycles where at least 4 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31Cycles at least 3 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Number of front end re-steers due to BPU mispredictionDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page sizedtlb_load_misses.pde_cache_missThis event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store missesMisses in ITLB that causes a page walk of any page sizeMisses in all ITLB levels that cause completed page walksCounts the number of ITLB flushes, includes 4k/2M/4M pagesNumber of ITLB page walker loads that hit in the L1+FBumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400002FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handlingRequests from the L2 hardware prefetchers that hit L2 cachel2_store_lock_rqsts.hit_mNot rejected writebacks that missed LLCCounts cycles MITE is delivered at least one uops. Set Cmask = 1Instruction cache, streaming buffer and victim cache missesLoads with latency value being above 16 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400001Cycles which a Uop is dispatched on port 0Cycles while L2 cache miss load* is outstandingPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise)umask=0x04,event=0x34umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc203f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dramoffcore_response.pf_l2_data_rd.llc_miss.any_dramtxl0p_power_cycles %event=0x7event=0xc,filter_band1=20Counts the number of cycles that the uncore was running at a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event)umask=0x4,period=200003,event=0x27l1d_blocks.bank_conflict_cyclesinv=1,umask=0x1,period=2000003,cmask=4,event=0x9cumask=0xa,period=2000003,event=0xacAll (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise)Memory page activates. Unit: uncore_imc umask=0xc,event=0x4unc_m_rpq_occupancyCounts the loads retired that get the data from the other core in the same tile in M state  Supports address when precise (Precise event)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010070umask=0x1,period=100007,event=0xb7,offcore_rsp=0x08000832f7Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080022Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeCounts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.bus_locks.l2_hit_near_tile_mCounts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.bus_locks.l2_hit_near_tile_e_foffcore_response.partial_writes.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080100offcore_response.demand_data_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000200Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M stateCounts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.partial_reads.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010002000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400044Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Localoffcore_response.uc_code_reads.ddr_farCounts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Faroffcore_response.pf_l2_rfo.mcdramCounts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800080offcore_response.any_request.ddroffcore_response.any_read.ddrCounts the number of branch instructions retired (Precise event)Counts the number of near indirect CALL branch instructions retired (Precise event)This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multipliesCounts all nukesCounts the number of unhalted core clock cyclesl1d_wb_l2.m_stateumask=0x8,period=100000,event=0x28L1 writebacks to L2 in M stateL2 data prefetches in M statel2_lines_in.anyumask=0xf,period=100000,event=0xf2L2 modified lines evicted by a prefetch requestumask=0x30,period=200000,event=0x24L2 instruction fetchesumask=0x4,period=200000,event=0xf0umask=0x8,period=100000,event=0x27mem_inst_retired.storesumask=0x40,period=200000,event=0xcbumask=0x10,period=2000000,event=0xf4umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4744offcore_response.any_rfo.io_csr_mmioOffcore writebacks to the IO, CSR, MMIO unitoffcore_response.corewb.llc_hit_no_other_coreoffcore_response.data_ifetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4777offcore_response.data_in.any_locationOffcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling coreoffcore_response.data_in.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x203Offcore demand data requests that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x702Offcore demand RFO requests that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8030umask=0x1,period=100000,event=0xb7,offcore_rsp=0x230offcore_response.pf_data.remote_cache_dramOffcore prefetch data reads satisfied by the LLC or local DRAMOffcore prefetch code reads satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3840Offcore prefetch RFO requests satisfied by a remote cacheComputational floating-point operations executedoffcore_response.any_rfo.local_dramOffcore prefetch data requests satisfied by a remote DRAMOffcore prefetch RFO requests satisfied by the local DRAMl1i.cycles_stalledumask=0x20,period=2000,event=0x89umask=0x40,period=20000,event=0x89Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)ssex_uops_retired.scalar_doubleinv=1,umask=0x1,period=2000000,cmask=1,event=0xd1uops_executed.core_stall_count_no_port5Cycles Uops are being retired (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100002period=50021,umask=0x4,event=0xd1offcore_response.other.l3_hit_e.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000028000Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020001Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3  Spec update: SKL057Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cachecmask=1,period=2000003,umask=0x1,event=0x48Counts duration of L1D miss outstanding in cyclesperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100004offcore_response.demand_code_rd.l3_hit_m.spl_hitoffcore_response.demand_code_rd.l3_hit_s.spl_hitoffcore_response.other.l3_hit_m.snoop_hitmoffcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200400002Cycles with less than 2 uops delivered by the front-endCounts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQRetired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)cmask=2,period=2000003,umask=0x2,event=0xa3Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise (Must be precise)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C400004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0044008000offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404008000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x007C400002period=2000003,umask=0x80,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C400002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000040001cmask=1,inv=1,period=2000003,umask=0x2,event=0xb1period=2000003,umask=0x40,event=0xa6A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled  Spec update: SKL091, SKL044 (Must be precise)Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization GuideInstructions per Branch (lower number means higher occurrence rate)Cache_Misses;OffcoreCounts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB)period=2000003,umask=0x10,event=0x49Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completedCounts the number of request from the L2 that were not accepted into the XQoffcore_response.any_code_rd.l2_miss.hit_other_core_no_fwdCounts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts any code reads (demand & prefetch) that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000040offcore_response.demand_rfo.l2_miss.snoop_missThis event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walksumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0040Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=2000000,event=0x60REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY RFO and RESPONSE = IO_CSR_MMIOREQUEST = CORE_WB and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITMREQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHEumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff04umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f80REQUEST = OTHER and RESPONSE = ANY_LOCATIONREQUEST = PF_DATA and RESPONSE = IO_CSR_MMIOREQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3044offcore_response.corewb.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf870umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5808umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2704Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or droppedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0491offcore_response.all_data_rd.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0004offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0400Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00120Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dramoffcore_response.demand_code_rd.l3_miss.remote_hitmoffcore_response.demand_data_rd.l3_miss.remote_hitmCounts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dramCounts all prefetch (that bring data to LLC only) RFOs that miss in the L3Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dramAverage IO (network or disk) Bandwidth Use for Writes [GB / sec]DRAM Underfill Read CAS Commands issued. Unit: uncore_imc PCI Express bandwidth reading at IIO, part 1. Unit: uncore_iio umask=0x01,event=0x5fIngress (from CMS) Allocations; IRQ. Unit: uncore_cha umask=0x04,event=0x5cCounts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) stateRsp*Fwd*WB Snoop Responses Received. Unit: uncore_cha unc_iio_clockticksPCIe Completion Buffer occupancy of completions with data: Part 2. Unit: uncore_iio Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0. Unit: uncore_iio unc_iio_data_req_by_cpu.peer_write.part2Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busPeer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2. Unit: uncore_iio unc_iio_txn_req_of_cpu.mem_read.part1Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio umask=0x8,event=0x10unc_i_faf_occupancyumask=0x2,event=0x2eunc_m2m_imc_writes.partialBL Ingress (from CMS) Allocations. Unit: uncore_m2m event=0x21Protocol header and credit FLITs received from any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unitThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100490offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_neededoffcore_response.all_reads.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000807F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_rfo.supplier_none.no_snoop_neededoffcore_response.demand_code_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_m.no_snoop_neededoffcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400002offcore_response.demand_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040080offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100080offcore_response.pf_l3_rfo.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_COREFraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)PMM_Read_BWperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000490ocr.all_reads.l3_miss_local_dram.any_snoopOCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREOCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_COREOCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_rfo.l3_miss_remote_hop1_dram.snoop_noneCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000001ocr.demand_data_rd.l3_miss.remote_hitmCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISSocr.demand_data_rd.l3_miss_local_dram.snoop_missocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwdocr.demand_rfo.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000010ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoopocr.pf_l2_rfo.l3_miss.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITMperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISSocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000100ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDOCR.ALL_DATA_RD.ANY_RESPONSE have any response typeOCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISSOCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONEocr.all_pf_data_rd.supplier_none.hit_other_core_fwdOCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit.snoop_hit_with_fwdOCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_reads.l3_hit_e.any_snoopocr.all_reads.supplier_none.no_snoop_neededOCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_rfo.supplier_none.snoop_missocr.demand_code_rd.l3_hit_f.snoop_noneocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_f.snoop_missocr.demand_data_rd.l3_hit_f.snoop_noneCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_s.any_snoopocr.demand_rfo.l3_hit_s.snoop_noneocr.other.l3_hit.snoop_missocr.other.l3_hit_e.hit_other_core_fwdCounts any other requests  OCR.OTHER.L3_HIT_F.ANY_SNOOPocr.other.l3_hit_f.hit_other_core_no_fwdocr.other.pmm_hit_local_pmm.any_snoopocr.other.pmm_hit_local_pmm.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORECounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_m.snoop_missCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_m.no_snoop_neededocr.pf_l2_rfo.supplier_none.snoop_missCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOPocr.pf_l3_rfo.l3_hit_e.any_snoopocr.pf_l3_rfo.l3_hit_e.snoop_noneocr.pf_l3_rfo.l3_hit_f.hitm_other_coreocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwdevent=0xe3TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_m2m_imc_reads.to_pmmCounts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructionsperiod=200003,umask=0xc8,event=0x24Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cacheperiod=100003,umask=0x80,event=0xc7idq.mite_cycles_anyperiod=100007,umask=0x1,event=0xc6,frontend=0x501006Counts Unfriendly TSX abort triggered by a nest count that is too deepCounts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.hwpf_l1d_and_swpf.dramTMA slots available for an unhalted logical processor. General counter - architectural eventCounts the number of uops executed from any threadperiod=100003,umask=0x2,event=0xa2period=500009,umask=0x80,event=0xduops_dispatched.port_0Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)Retired demand load instructions which missed L3 but serviced from remote IXP memory as data sources  Supports address when precise (Precise event)Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entriesumask=0x02,event=0x20PMM Write Queue Inserts. Unit: uncore_imc unc_cha_tor_inserts.ia_hit_rfounc_cha_tor_occupancy.ia_miss_crdTOR Occupancy : All requests from IO Devices. Unit: uncore_cha umask=0xC887FE01,event=0x35unc_cha_tor_inserts.ia_crdumask=0xC816FE01,event=0x36umask=0xC886FE01,event=0x35umask=0xC8877E01,event=0x35TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha fc_mask=0x07,ch_mask=0x04,umask=0x80,event=0x84fc_mask=0x07,ch_mask=0x20,umask=0x80,event=0x84fc_mask=0x04,ch_mask=0x04,umask=0x03,event=0xc2unc_iio_comp_buf_inserts.cmpd.part5PCIe Completion Buffer Inserts of completions with data: Part 5. Unit: uncore_iio fc_mask=0x04,ch_mask=0x80,umask=0x03,event=0xc2PCIe Completion Buffer Inserts of completions with data: Part 7. Unit: uncore_iio PCIe Completion Buffer Occupancy of completions with data : Part 5. Unit: uncore_iio PCIe Completion Buffer Occupancy of completions with data : Part 1. Unit: uncore_iio Multi-socket cacheline Directory Lookups : Found in I state. Unit: uncore_m2m unc_upi_txl_flits.all_dataCounts cacheable memory requests that access the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filterCounts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/Mmem_bound_stalls.store_buffer_fullCounts the total number of load uops retired  Supports address when precise (Precise event)period=200003,umask=0x2,event=0x63Counts the number of hardware interrupts received by the processorCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of responsetopdown_fe_bound.itlbperiod=200003,umask=0xeb,event=0xc4Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter (Precise event)event=0x91Decoder Overrides Existing Branch Prediction (speculative)umask=0x10,event=0x60All L2 Cache Requests (Breakdown 2 - Rare). Bus lock responseumask=0x20,event=0x64event=0x1d0remote_outbound_data_controller_0L1 DTLB Miss of a page of 4K sizels_inef_sw_pref.mab_mch_cntrecommendedl2_cache_misses_from_dc_missesl2_cache_misses_from_l2_hwpfall_l2_cache_hitsL2 DTLB Misses & Data page walksFloating Point Dispatch Faults. YMM spill faultumask=0x40,event=0x43Demand Data Cache Fills by Data Source. DRAM or IO from different dieDemand Data Cache Fills by Data Source. DRAM or IO from this thread's diels_refills_from_sys.ls_mabresp_lcl_cachels_hw_pf_dc_fill.ls_mabresp_rmt_dramumask=0x04,event=0xaede_dis_dispatch_token_stalls0.sc_agu_dispatch_stallThe number of times the instruction decoder overrides the predicted targetRetired Ops. Use macro_ops_retired insteadThe number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are countedls_dmnd_fills_from_sys.ext_cache_localCPU_CLK_UNHALTED_REFFR_NUMBER_OF_BREAKPOINTS_FOR_DR3PMNC_SW_INCRMEM_WRITEEVENT_06HEVENT_42HEVENT_67HEVENT_6AHEVENT_81HEVENT_8EHEVENT_A9HEVENT_C1HSOFTWARE_JAVA_BYTECODEDMBL1D_TLB_REFILLBR_MIS_PREDBUS_ACCESS_NORMALSTALL_FRONTENDL1D_CACHE_REFILL_INNERL2CACHE_READ_HITTAGCACHE_WRITE_HITTAGCACHEMASTER_READ_REQJTLB_DMISSSTORE_COND_COMPLETEDREQUEST_LATENCYICACHE_MISSESAGEN_NO_ISSUES_CYCLESWBB_OVER_50_FULLFPU_INSNSALU_DSP_SATURATION_INSNSSISSUEIIITLBMTVRSAVE_INSTR_COMPLETEDLSU_INSTR_COMPLETEDVR_STALLSMISPREDICTED_BRANCHESL3_INSTR_CACHE_MISSESMARKED_STORE_COMPLETEDFXU0_IDLE_FXU1_BUSYPMC0_OVERFLOWFPU_DENORM_INPUT_CYCLESadd-pipe-excluding-junk-opsic-fillpage-hit%s:	%s
pmu: %s
LONGEST_LAT_CACHE.MISS%s, "tid": "%d"}
GenuineIntel-6-56inst_retired.any / cpu_clk_unhalted.threadAverage CPU UtilizationC3 residency percent per coreC6_Core_Residency(cstate_core@c7\-residency@ / msr@tsc@) * 100This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are countedRFO requests to L2 cacheumask=0x42,period=100003,event=0xd0umask=0x7,period=100003,event=0xf1umask=0x15,period=2000006,event=0xc7fp_arith_inst_retired.singleumask=0x3c,period=2000004,event=0xc7This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalidThis counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is emptyumask=0x10,period=2000003,event=0x79Cycles MITE is delivering 4 UopsThis event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit)Cycles with less than 3 uops delivered by the front endNumber of times we entered an HLE region
 does not count nested transactionsNumber of times HLE abort was triggered (PEBS) (Precise event)Number of times an HLE execution aborted due to HLE-unfriendly instructionscpl_cycles.ring0_transThis event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventsumask=0x3,period=2000003,event=0Not software-prefetch load dispatches that hit FB allocated for hardware prefetchThis event counts taken speculative and retired indirect branches excluding calls and return branchesbr_inst_exec.taken_indirect_near_callumask=0xd0,period=200003,event=0x88br_misp_exec.all_branchesuops_executed_port.port_3uops_executed_port.port_4_coreCycles stalled due to re-order buffer fullumask=0x5,cmask=5,period=2000003,event=0xa3cycle_activity.stalls_mem_anycycle_activity.stalls_l1d_pendinguops_retired.retire_slotsThis is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used (Precise event)br_misp_retired.conditionalThis event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT registerMMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.data_llc_prefetchllc_references.code_llc_prefetchllc_references.streaming_partialumask=0x1,event=0x35,filter_opc=0x19ePCIe read current. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_h_requests.writesPre-charge for writes. Unit: uncore_imc dtlb_store_misses.walk_durationept.walk_cyclesumask=0x10,period=2000003,event=0x4fpage_walker_loads.itlb_l2umask=0x22,period=2000003,event=0xbc( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPUinst_retired.any / br_inst_retired.near_takenBranches;Fetch_BW;PGORough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructionsInstructions per Load (lower number means higher occurance rate)inst_retired.any / br_misp_retired.all_branches64 * l1d.replacement / 1000000000 / duration_timeL2 cache misses per kilo instruction for all request types (including speculative)1000 * l2_rqsts.miss / inst_retired.anyL2HPKI_Allumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0010offcore_response.pf_l2_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0040offcore_response.pf_l3_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200028000offcore_response.all_pf_data_rd.l3_hit.snoop_hitmoffcore_response.all_data_rd.supplier_none.snoop_noneNumber of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event)  Spec update: BDM30SSE* FP micro-code assist when output value is invalid. (Precise Event)umask=0x18,period=2000003,cmask=1,event=0x79Counts randomly selected loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000004offcore_response.corewb.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000010offcore_response.pf_l2_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000040offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwdoffcore_response.all_pf_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000240offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000091Number of cycles using always true condition applied to  PEBS uops retired event (Precise event)This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired  Spec update: BDW98umask=0x44,event=0x22L3 Lookup read request that access cache and found line in M-stateSocket actual clocks when any core is active on that socketThis event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)Retired load uops with locked access  Supports address when precise.  Spec update: BDM35 (Precise event)This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)l2_ifetch.self.e_statel2_ld.self.any.mesiumask=0x48,period=200000,event=0x2bumask=0x4f,period=200000,event=0x2dl2_reject_busq.self.demand.s_stateumask=0x83,period=2000000,event=0x40l1d_cache.replmumask=0x0,period=2000000,event=0xcfprefetch.prefetcht2bus_request_outstanding.all_agentsNumber of Bus Not Ready signals assertedbus_drdy_clocks.all_agentsumask=0x20,period=200000,event=0x62umask=0x40,period=200000,event=0x64umask=0xe0,period=200000,event=0x67bus_trans_pwr.all_agentsbus_trans_burst.selfbus_hit_drv.all_agentscpu_clk_unhalted.refbr_inst_type_retired.cond_takenbr_inst_retired.pred_not_takenbr_inst_retired.takenL0 DTLB misses due to store operationsLoad uops retired that hit L2 (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that miss the L1 data cache  Supports address when precise (Must be precise)offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000022Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.any_request.l2_miss.hit_other_core_no_fwdoffcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_neededCounts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor moduleCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_neededoffcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwdCounts data cache lines requests by software prefetch instructions that hit the L2 cacheoffcore_response.pf_l2_rfo.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000020Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.anyCounts hardware interrupts received by the processorCycles hardware interrupts are maskedCounts branch instructions retired for all branch types.  This is an architectural performance event (Must be precise)br_inst_retired.rel_callCounts core cycles if either divide unit is busyCounts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010010Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)machine_clears.page_faultdtlb_store_misses.walk_completed_1gbCounts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation.  The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs).  Average cycles per walk can be calculated by dividing the count by number of walksCounts all L2 HW prefetcher requests that missed L2This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cacheCycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61Demand Data Read requests sent to uncore  Spec update: HSD78hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_reads.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l2_code_rd.l3_hit.any_responseoffcore_response.demand_data_rd.l3_hit.hitm_other_coreCounts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00091This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uopsCycles per core when uops are executed in port 4Cycles with pending L2 cache miss loads  Spec update: HSD78Cycles with pending L2 miss loads. Set Cmask=2 to count cycle  Spec update: HSD78Number of loads missed L2Mispredicted branch instructions at retirementUnit: uncore_cbox L3 Lookup external snoop request that access cache and found line in M-stateumask=0x46,event=0x34Retired load uops misses in L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)umask=0x4,period=100003,event=0xd3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00004inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xc2l2_lines_out.pf_cleanfp_comp_ops_exe.x87Number of DSB to MITE switchesivb metrics1000 * mem_load_uops_retired.llc_miss / inst_retired.anyumask=0x3,edge=1,period=2000003,cmask=1,event=0xdLLC lookup request that access cache and found line in I-stateumask=0x06,event=0x34Misses in all TLB levels that caused page walk completed of any size by demand loadsCounts demand data reads that hit in the LLC and sibling core snoop returned a clean responseunc_q_txl_flits_g0.dataRead requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc (unc_p_freq_band0_cycles / unc_p_clockticks) * 100.Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu unc_p_freq_band0_transitions(unc_p_freq_ge_2000mhz_cycles / unc_p_clockticks) * 100.event=0xd,filter_band2=30Counts the number of times that the uncore transitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event)Retired load uops which data sources were data hits in LLC without snoops requiredNumber of AVX-256 Computational FP double precision uops issued this cyclepartial_rat_stalls.flags_merge_uopbr_misp_retired.not_takenUops dispatched per threadumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132f7offcore_response.any_data_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000088000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002001000offcore_response.any_data_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000004offcore_response.uc_code_reads.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010001000Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l2_code_rd.l2_hit_near_tileoffcore_response.partial_reads.l2_hit_near_tileoffcore_response.partial_writes.l2_hit_far_tileCounts the number of times the machine clears due to memory ordering hazardsoffcore_response.any_pf_l2.ddr_farCounts any Prefetch requests that accounts for data responses from DRAM FarCounts any request that accounts for data responses from DRAM Farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080808000Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_software.mcdram_faroffcore_response.bus_locks.ddr_nearoffcore_response.pf_l2_code_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400020umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180608000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600022offcore_response.any_code_rd.mcdramoffcore_response.pf_l2_rfo.ddrl1d_all_ref.anyL1 data cacheable reads and writesl1d_cache_ld.e_stateumask=0x10,period=200000,event=0x26L2 lines allocated in the S stateAll L2 missesumask=0x1,period=100000,event=0x27L2 demand store RFOs in M statemem_uncore_retired.other_core_l2_hitmCacheable loads delayed with L1D block codemem_inst_retired.latency_above_threshold_256umask=0x10,period=200,event=0xb,ldlat=0x200Offcore data reads satisfied by the IO, CSR, MMIO unitAll offcore RFO requestsoffcore_response.any_rfo.remote_cache_hitmoffcore_response.corewb.local_cacheOffcore writebacks that HITM in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x277offcore_response.data_ifetch.llc_hit_other_core_hitmOffcore code or data read requests satisfied by the LLCoffcore_response.data_ifetch.remote_cacheOffcore code or data read requests satisfied by a remote cacheOffcore code or data read requests that HITM in a remote cacheoffcore_response.demand_data.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x101offcore_response.other.any_cache_dramoffcore_response.other.io_csr_mmiooffcore_response.pf_data.io_csr_mmioOffcore prefetch data requests satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4710offcore_response.pf_ifetch.local_cacheOffcore prefetch RFO requests satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4770Transitions from Floating Point to MMX instructionssimd_int_64.packed_shiftumask=0x1,period=100000,event=0xb7,offcore_rsp=0x40FFoffcore_response.any_request.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6008Offcore code or data read requests satisfied by any DRAMOffcore code or data read requests satisfied by a remote DRAMOffcore demand data requests satisfied by the local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6002umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6010umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4040umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4020umask=0x1,period=2000000,event=0x6cumask=0x1,period=2000000,event=0xf6BACLEAR asserted, regardless of cause umask=0x10,period=2000,event=0x89cpu_clk_unhalted.ref_pLength Change Prefix stall cyclesFPU control word write stall cyclesCycles Uops executed on ports 0-4 (core count)Uops executed on port 0Uops executed on port 3 (core count)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400108000offcore_response.demand_data_rd.l3_hit_m.snoop_not_neededoffcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001C8000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020001mem_inst_retired.split_storesCounts L2 cache hits when fetching instructions, code readsoffcore_response.demand_data_rd.l3_hit_m.snoop_hitmCounts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000408000offcore_response.demand_code_rd.l3_hit_s.any_snoopmem_inst_retired.lock_loadsperiod=100007,umask=0x21,event=0xd0period=100003,umask=0x1,event=0xb7offcore_response.demand_data_rd.l3_hit_e.snoop_missCounts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSperiod=100007,umask=0x1,event=0xc6,frontend=0x400806Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C400002offcore_requests.l3_miss_demand_data_rdCounts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer  Spec update: SKL089Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000108000period=2000003,umask=0x2,event=0x32period=2000003,umask=0x4,event=0x32cmask=1,edge=1,period=100003,umask=0x1,event=0xc3Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not emptycmask=1,period=2000003,umask=0x2,event=0xb1Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventscpu_clk_unhalted.ring0_transperiod=2000003,umask=0x2,event=0xb1cmask=12,period=2000003,umask=0xc,event=0xa3period=2000003,umask=0x4,event=0xa6cmask=1,period=2000003,umask=0x1,event=0xa3Summary;TopDownL1Memory_BW;SoCCounts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultCounts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultoffcore_response.any_code_rd.l2_miss.anyCounts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedThis event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlersThis event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.  Background: Modern microprocessors employ extensive pipelining and speculative techniques.  Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced.  A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires.  This counter measures the number of completed instructions.  The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_PRetired store uops that miss the STLB. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event)offcore_response.all_pf_code_rd.llc_hit.no_snoop_neededCounts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch RFOs that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0122offcore_response.pf_l2_rfo.llc_hit.snoop_missCounts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_code_rd.llc_hit.no_snoop_neededCounts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0100REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSECounts all demand & prefetch RFOs that miss the LLC  and the data returned from dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400010Cycles offcore reads busyCycles offcore demand code read busyREQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x10ffumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff22REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5004REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x750REQUEST = PF_RFO and RESPONSE = LOCAL_CACHEumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5070REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISSoffcore_response.demand_ifetch.any_dram_and_remote_fwdREQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDdtlb_load_misses.large_walk_completedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0490Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_data_rd.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00120Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dramoffcore_response.demand_code_rd.l3_miss.remote_hit_forwardCounts demand data reads that miss the L3 and the data is returned from local dramCounts all demand data writes (RFOs) that miss in the L3Branches;FetchBW;PGOInsTypeCacheMisses;OffcoreStreaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x83LLC_MISSES.PCIE_WRITECHA to iMC Full Line Writes Issued; Full Line Non-ISOCH. Unit: uncore_cha Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channelsumask=0x02,event=0x37Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data)RspSFwd Snoop Responses Received. Unit: uncore_cha unc_iio_comp_buf_inserts.cmpd.part0fc_mask=0x4,ch_mask=0x02,umask=0x03,event=0xc2fc_mask=0x04,umask=0x02,event=0xd5Read request for 4 bytes made by the CPU to IIO Part0. Unit: uncore_iio Read request for 4 bytes made by the CPU to IIO Part3. Unit: uncore_iio Write request of 4 bytes made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x83fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc1Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc1fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x84Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busPeer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRPunc_m2m_directory_lookup.state_iunc_m2m_directory_update.a2sPrefecth requests that got turn into a demand request. Unit: uncore_m2m Data Response packets that go direct to core. Unit: uncore_upi ll Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unitoffcore_response.all_data_rd.l3_hit_e.no_snoop_neededoffcore_response.all_data_rd.l3_hit_m.snoop_missoffcore_response.all_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100491offcore_response.all_data_rd.supplier_none.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwdoffcore_response.all_pf_data_rd.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080120offcore_response.all_pf_rfo.l3_hit_f.any_snoopoffcore_response.all_pf_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C07F7offcore_response.all_reads.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000407F7offcore_response.all_reads.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.demand_data_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080010offcore_response.pf_l2_data_rd.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080010offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200020offcore_response.pf_l2_rfo.l3_hit_f.snoop_missoffcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwdoffcore_response.pf_l2_rfo.l3_hit_m.no_snoop_neededoffcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020020This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200080offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_m.snoop_missoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0100offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.supplier_none.hitm_other_coreocr.all_data_rd.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000490OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREOCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss_local_dram.snoop_noneocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.all_rfo.l3_miss.snoop_missocr.demand_code_rd.l3_miss.remote_hitmCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISSCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000001Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss.hit_other_core_no_fwdocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_noneocr.other.l3_miss_remote_hop1_dram.no_snoop_neededCounts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000010ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededocr.pf_l2_rfo.l3_miss.any_snoopCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONECounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000100This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_coreoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_missoffcore_response.demand_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.other.l3_miss.remote_hit_forwardThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_neededoffcore_response.pf_l2_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_missocr.all_data_rd.l3_hit_s.hitm_other_coreOCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDOCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISSOCR.ALL_PF_RFO.ANY_RESPONSE have any response typeocr.all_pf_rfo.l3_hit.no_snoop_neededOCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOPocr.all_reads.l3_hit_e.hit_other_core_no_fwdocr.all_reads.l3_hit_m.hit_other_core_fwdOCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_reads.pmm_hit_local_pmm.snoop_noneocr.all_rfo.l3_hit_m.any_snoopocr.all_rfo.l3_hit_m.no_snoop_neededOCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_COREocr.demand_code_rd.l3_hit_e.snoop_missocr.demand_code_rd.supplier_none.any_snoopocr.demand_code_rd.supplier_none.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOPocr.demand_data_rd.l3_hit_s.no_snoop_neededocr.demand_data_rd.supplier_none.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_s.no_snoop_neededocr.other.l3_hit_s.snoop_missocr.pf_l1d_and_sw.l3_hit.snoop_missocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwdocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_noneocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_noneocr.pf_l2_rfo.l3_hit_e.any_snoopocr.pf_l2_rfo.supplier_none.snoop_noneCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_s.snoop_missCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONECounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_f.snoop_noneunc_m_pmm_rpq_occupancy.allumask=0x4,event=0xd3M2M Reads Issued to iMC; All, regardless of priorityunc_m2m_tag_hit.nm_ufill_hit_dirtyperiod=100021,umask=0x4,event=0xd1Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)inst_retired.any / cpu_clk_unhalted.distributedperiod=100003,umask=0x2,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC08000Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cacheCounts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184008000Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.hwpf_l2_data_rd.l3_hit.snoop_not_neededocr.hwpf_l1d_and_swpf.l3_hit.snoop_missCounts the number of PREFETCHW instructions executedcmask=2,period=1000003,umask=0x40,event=0xa6Uops that RAT issues to RSCounts mispredicted conditional branch instructions retired (Precise event)Counts cycles when at least 1 micro-op is executed from any thread on physical coreTMA slots where uops got droppedEstimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasonscmask=5,period=2000003,umask=0x21,event=0xa6umask=0x01,event=0xd3All DRAM read CAS commands issued (including underfills). Unit: uncore_imc unc_m_pre_count.pgtHalf clockticks for IMC. Unit: uncore_imc unc_m_act_count.allumask=0x1C,event=0x2PMM Commands : All. Unit: uncore_imc PMM Commands : Writes. Unit: uncore_imc TOR Inserts : CRds issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_llcprefrfounc_cha_tor_inserts.ia_specitomTOR Inserts : SpecItoMs issued by iA Cores. Unit: uncore_cha TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC. Unit: uncore_cha TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC. Unit: uncore_cha unc_iio_txn_req_of_cpu.cmpd.part0unc_iio_txn_req_by_cpu.mem_write.part7Multi-socket cacheline Directory Lookups : Found in any state. Unit: uncore_m2m CMS Clockticks. Unit: uncore_m2pcie Valid Flits Sent : All Non Data. Unit: uncore_upi ll Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss)Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBmem_bound_stalls.ifetch_dram_hitperiod=2000003,umask=0x8,event=0xc2Counts the number of memory ordering machine clears triggered by a snoop from an external agenttopdown_bad_speculation.mispredicttopdown_fe_bound.branch_resteerperiod=1000003,umask=0x4,event=0x71Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2Counts the number of Extended Page Directory Entry missesitlb_misses.pde_cache_missumask=0x20,event=0x60l2_request_g1.cacheable_ic_readLS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requestsumask=0x09,event=0x64l2_fill_pending.l2_fill_busyL2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf insteadl2_pf_miss_l2_l3Retired Near Returnsumask=0x38,event=0x1c7Total number uOps assigned to all fpu pipesfp_retx87_fp_ops.add_sub_opsumask=0xff,event=0x3Number of Ops that are candidates for optimization (have Z-bit either set or pass)umask=0x01,event=0x25umask=0x01,event=0x41Total Page Table Walks DC Type 1Software Prefetch Instructions (3DNow PREFETCHW instruction) DispatchedThe number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hitd_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)L2 ITLB Misses & Instruction page walksbp_l1_tlb_fetch_hit.if2mumask=0x04,event=0xeSoftware Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHWls_sw_pf_dc_fill.ls_mabresp_rmt_cacheumask=0x10,event=0x5aOps dispatched from either the decoders, OpCache or bothCore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss insteadAll L3 Request Types. All L3 cache Requests. Unit: uncore_l3pmc Demand Data Cache Fills by Data Source. From Local L2 to the coreAny Data Cache Fills by Data Source. From CCX Cache in different Nodels_hw_pf_dc_fills.mem_io_localCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP schedulerMacro-ops RetiredDC_L1_DTLB_MISS_AND_L2_DTLB_HITFR_RETIRED_NEAR_RETURNS_MISPREDICTEDINSTR_SPECL2_CACHE_MISSEVENT_31HEVENT_7AHEVENT_A7HEVENT_E6HEVENT_E7HEVENT_F9HINSTR_CACHE_DEPENDENT_STALLMAIN_TLB_MISS_STALLPLE_CACHE_LINE_REQ_SKIPPEDL1D_CACHE_REFILLL2D_CACHE_REFILLRC_ST_SPECMEM_BYTE_WRITEMDU_STALL_CYCLESPDTRACE_BACK_STALLSIODQ_FULL_DR_STALLSALU_NO_ISSUES_CYCLESBRANCH_LIKELY_INSNSSYSTEM_EVENT_6LDQ_25_50_FULLISSUEWDATBADDL2LMLDSLMSTSDTLBBRANCH_LINK_STAC_PREDICTEDEIEIO_INSTR_COMPLETEDL1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLDLSU_MISALIGN_STORE_COMPLETEDITLB_NON_SPECULATIVE_MISSESTLBIE_SNOOPSSTORE_MERGE_GATHERDST_STREAM_3_CACHE_LINE_FETCHESPREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCHGCT_EMPTY_BY_SRQ_FULLREJECT_COMPLETION_STALLL3_INSTR_MISSTOTAL_TRANSLATEDADDRESS_COLLISION_CYCLESBIU_MASTER_INSTR_SIDE_REQUESTSCYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULLnonpostwrszbyteINTEL_CLINTEL_COREINTEL_BROADWELLRESOURCE_STALLS_ANY{"type": "dropnotify"}
{"type": "thr_exit"%s, "pmcid": "0x%08x", "event": "0x%08x", "flags": "0x%08x", "rate": "%jd"}
GenuineIntel-6-35uops_retired.retire_slots / inst_retired.anycpu_clk_unhalted.thread / cpu_clk_unhalted.ref_tscC3_Core_Residencyumask=0x27,period=200003,event=0x24umask=0xe2,period=200003,event=0x24Demand RFO requests including regular RFOs, locks, ItoMOffcore requests buffer cannot take more entries for this thread coreumask=0x8,period=100003,event=0xc1fp_arith_inst_retired.scalar_singleumask=0x4,period=2000003,event=0xc7Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequenceridq.mite_all_uopsDecode Stream Buffer (DSB)-to-MITE switch true penalty cyclesNumber of times a TSX Abort was triggered due to commit but Lock Buffer not emptyumask=0x10,period=2000003,event=0x5drtm_retired.commitumask=0x1,period=100003,event=0xcd,ldlat=0x4This event counts loads with latency value being above eight  Spec update: BDM100, BDM35 (Must be precise)pipelineCases when loads get true Block-on-Store blocking code preventing store forwardingThis event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useCounts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issuesThis event counts taken speculative and retired direct near callsumask=0xc1,period=200003,event=0x88umask=0x81,period=200003,event=0x89umask=0x3,period=2000003,event=0xa0umask=0x1,any=1,period=2000003,event=0xa1Cycles while memory subsystem has an outstanding loadumask=0x6,cmask=6,period=2000003,event=0xa3cycle_activity.stalls_l1d_missuops_executed.cycles_ge_3_uops_execPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: BDM11, BDM55 (Must be precise)umask=0x4,period=100003,event=0xc3This is a precise version (that is, uses PEBS) of the event that counts return instructions retired (Precise event)llc_misses.rfo_llc_prefetchwrite requests to local home agent. Unit: uncore_ha unc_m_dclockticksThis is an occupancy event that tracks the number of cores that are in C3.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPUinst_retired.any / mem_uops_retired.all_storesBranch_Misprediction_CostL2MPKIL2 cache hits per kilo instruction for all request types (including speculative)( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / 1000000000 ) / duration_timeoffcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwdoffcore_response.pf_l2_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020200offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020091Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event)  Spec update: BDM30This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist interventionumask=0x30,edge=1,period=2000003,cmask=1,event=0x79umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000001offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwdoffcore_response.pf_l2_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_noneoffcore_response.all_data_rd.l3_miss_local_dram.snoop_hitmoffcore_response.all_rfo.l3_miss.snoop_missumask=0x1,period=2000003,cmask=4,event=0xa8umask=0x1,period=2000003,cmask=1,event=0xa8unc_cbo_xsnp_response.hitm_xcoreumask=0x11,event=0x34L3 Lookup write request that access cache and found line in M-stateunc_cbo_cache_lookup.read_esumask=0x01,cmask=1,event=0x80DRAM_Parallel_ReadsMiss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event)This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event)offcore_response.all_reads.llc_miss.remote_hitmoffcore_response.all_code_rd.llc_miss.local_draml2_lines_in.self.anyumask=0x40,period=200000,event=0x25umask=0x70,period=200000,event=0x26umask=0x44,period=200000,event=0x2al2_lock.self.s_statel2_data_rqsts.self.i_statel2_data_rqsts.self.mesiAll read requests from L1 instruction and data cachesL2 cache requestsumask=0x5f,period=200000,event=0x2eumask=0x1,period=2000000,event=0xc7simd_comp_inst_retired.scalar_doubleumask=0x1,period=200000,event=0x80Partial write bus transactionumask=0x40,period=200000,event=0x6freissue.any.ardiv.arAll indirect branches that have a return mnemonicPeriods no micro-ops retiredRetired taken branch instructionsumask=0x81,period=200000,event=0x3umask=0x4,period=200000,event=0xcbCounts memory requests originating from the core that miss in the L2 cacheCounts memory requests originating from the core that reference a cache line in the L2 cachemem_uops_retired.splitCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003091Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers that hit the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000020Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cacheCounts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x2,period=200003,event=0xc3fetch_stall.allInstructions retired (Fixed event)Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise)Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise)Retired near return instructions (Precise event capable) (Must be precise)umask=0xfe,period=200003,event=0xc4Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.full_streaming_stores.outstandingCounts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor moduleoffcore_response.any_pf_data_rd.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003091Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violationCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page faultumask=0x8,period=2000003,event=0x85Number of instruction fetches that hit the L2 cacheDemand requests to L2 cache  Spec update: HSD78Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Counts cycles the IDQ is empty  Spec update: HSD135offcore_response.all_reads.l3_miss.local_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400001Cycles which a uop is dispatched on port 1 in this threadExecution stalls due to L1 data cache missesStore miss in all TLB levels causes a page walk that completes. (1G)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00001Retired load uops that miss the STLB. (Precise Event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event)Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.demand_rfo.llc_hit.no_snoop_neededCounts all demand data readsumask=0x40,period=2000003,event=0x10umask=0x2,period=2000003,event=0x11Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB missNumber of flags-merge uops being allocatedumask=0x30,any=1,period=2000003,event=0xa1umask=0x4,period=100003,event=0x5foffcore_response.pf_l2_data_rd.llc_miss.remote_hit_forwardoffcore_response.pf_l2_data_rd.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20080Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial. Unit: uncore_cbox Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequentlypartial_rat_stalls.slow_lea_windowumask=0x8,period=100003,event=0x7resource_stalls2.all_prf_controlumask=0x20,period=2000003,cmask=1,event=0x59event=0x80Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache missesumask=0x4,period=100007,event=0x4offcore_response.any_pf_l2.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x10004032f7umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400200Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010040offcore_response.pf_l2_rfo.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000020020umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000100offcore_response.any_data_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004003091Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in S stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800183091Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800044offcore_response.any_data_rd.ddr_nearoffcore_response.any_request.mcdram_nearCounts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.uc_code_reads.ddr_nearCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200001L2 load hitsumask=0x2,period=200000,event=0x24umask=0xc0,period=200000,event=0x24All L2 prefetchesl2_transactions.prefetchl2_write.rfo.mesiumask=0x2,period=2000000,event=0xbMemory instructions retired above 128 clocks (Precise Event)mem_inst_retired.latency_above_threshold_512Memory instructions retired above 8 clocks (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1011offcore_response.any_request.llc_hit_other_core_hitmOffcore RFO requests satisfied by the IO, CSR, MMIO unitOffcore RFO requests satisfied by a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF08offcore_response.corewb.remote_cacheOffcore writebacks to a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1833umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF03All offcore demand data readsoffcore_response.demand_data_rd.llc_hit_no_other_coreoffcore_response.demand_data_rd.remote_cache_hitmoffcore_response.demand_ifetch.any_locationOffcore demand code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_ifetch.remote_cache_hitoffcore_response.demand_rfo.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF80Offcore prefetch data requests that HIT in a remote cacheOffcore prefetch code reads that HIT in a remote cacheOffcore prefetch RFO requests satisfied by any cache or DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF70offcore_response.prefetch.llc_hit_no_other_coreOffcore prefetch requests satisfied by the LLC and not found in a sibling coreoffcore_response.prefetch.llc_hit_other_core_hitmOffcore prefetch requests satisfied by the LLC or local DRAM128 bit SIMD integer logical operationssimd_int_64.packed_mpyumask=0x1,period=100000,event=0xb7,offcore_rsp=0x60FFOffcore requests satisfied by a remote DRAMoffcore_response.any_rfo.remote_dramOffcore data reads, RFO's and prefetches statisfied by the local DRAMOffcore demand data reads satisfied by a remote DRAMoffcore_response.demand_rfo.any_llc_missOffcore other requests satisfied by any DRAMoffcore_response.pf_data_rd.remote_draml1i.readsumask=0xf,period=2000000,event=0xd2umask=0x1,period=2000000,event=0xd4arith.divumask=0x2,period=20000,event=0xc4br_misp_exec.anyMispredicted indirect non call branches executedild_stall.anyumask=0x1,period=2000000,event=0x1einst_retired.mmxresource_stalls.loadumask=0x2,period=2000000,event=0xa2DTLB load missesumask=0x10,period=200000,event=0x49period=100003,umask=0x4,event=0xb0Retired load instructions with L3 cache hits as data sources  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040004period=200003,umask=0x22,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080001Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncoreoffcore_response.other.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020004mem_inst_retired.stlb_miss_loadsmem_load_retired.fb_hitNumber of cache line split locks sent to uncoreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020004period=200003,umask=0xc4,event=0x24period=2000003,umask=0x2,event=0x48period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080001period=2000003,umask=0x2,event=0x60mem_inst_retired.stlb_miss_storescmask=4,period=2000003,umask=0x1,event=0x9cperiod=100007,umask=0x1,event=0xc6,frontend=0x400206Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularityperiod=2000003,umask=0x40,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000080001period=2000003,umask=0x20,event=0xc8period=100003,umask=0x1,event=0xb7,offcore_rsp=0x203C400001sw_prefetch_access.prefetchwDemand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCounts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event)exe_activity.bound_on_storesany=1,period=2000003,umask=0x1,event=0xdcmask=2,period=2000003,umask=0x2,event=0xb1period=400009,umask=0x4,event=0xc5This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Boundidq_uops_not_delivered.core / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]period=100003,umask=0x4,event=0x49Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific)Load miss in all TLB levels causes a page walk that completes. (All page sizes)Counts the number of request that were not accepted into the L2Q because the L2Q is FULLLoad uops that split cache line boundary (Precise event)This event counts the number of store ops retiredoffcore_response.any_code_rd.l2_miss.snoop_missCounts code reads generated by L2 prefetchers that miss L2The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance.  Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources.  When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidthDuration of I-side page-walks in core cyclesCounts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCounts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedREQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSEoffcore_response.pf_ifetch.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400122offcore_response.pf_llc_data_rd.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400004This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel® 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issuedOffcore RFO requestsoffcore_requests.demand.rfoumask=0x2,period=2000000,event=0x60Outstanding offcore demand RFOsCycles offcore demand RFOs busyREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIToffcore_response.data_in.local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff01umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5080REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAMREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAMREQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf820REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAMREQUEST = PREFETCH and RESPONSE = ANY_LLC_MISSsnoopq_requests.invalidateperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0491Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresNumber of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts all demand & prefetch data reads that miss the L3 and the data is returned from remote dramCounts prefetch RFOs that miss the L3 and the data is returned from remote dramCounts all demand code reads that miss in the L3Counts all demand code reads that miss the L3 and the data is returned from local or remote dramoffcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800004Counts demand data reads that miss in the L3offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00100core_power.lvl2_turbo_licenseCore cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo scheduleSMT;TmaL1( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single ) / cpu_clk_unhalted.threadMemoryBW;SoCIO_Write_BWunc_m_cas_count.wr_wmmWrite Pending Queue Allocations. Unit: uncore_imc unc_cha_core_snp.core_gtoneunc_cha_llc_victims.total_fCounts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineunc_iio_comp_buf_occupancy.cmpd.part2fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc0Write request of 4 bytes made to IIO Part2 by the CPU. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part3fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc1unc_iio_txn_req_of_cpu.mem_write.part2unc_iio_txn_req_of_cpu.peer_write.part0unc_iio_txn_req_of_cpu.peer_write.part2Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts reads in which direct to core transactions (which would have bypassed the CHA) were overriddenevent=0x57event=0x2Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdownCounts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.all_pf_data_rd.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040120This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISSoffcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0001offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200002offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C8000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200208000offcore_response.other.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080080This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100100OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_COREocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwdOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDOCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_pf_data_rd.l3_miss_local_dram.any_snoopOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000490ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDOCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISSocr.all_rfo.l3_miss_local_dram.no_snoop_neededocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.all_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000004ocr.demand_data_rd.l3_miss.hit_other_core_no_fwdocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000001Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000400Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_missCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000100This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_pf_rfo.l3_miss.hit_other_core_fwdoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.all_reads.l3_miss_local_dram.any_snoopoffcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwdoffcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwdoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoopoffcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwdoffcore_response.pf_l2_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwdoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_neededocr.all_data_rd.l3_hit_e.any_snoopocr.all_data_rd.l3_hit_e.no_snoop_neededOCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOPOCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.all_data_rd.l3_hit_s.snoop_noneOCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISSOCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONEOCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONEocr.all_pf_rfo.supplier_none.hit_other_core_fwdOCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_HIT_S.SNOOP_MISSocr.all_rfo.l3_hit_f.no_snoop_neededOCR.ALL_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_S.ANY_SNOOPOCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_rfo.supplier_none.hitm_other_coreOCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISSocr.demand_code_rd.l3_hit.hitm_other_coreocr.demand_code_rd.l3_hit.snoop_noneocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwdocr.demand_data_rd.l3_hit_e.any_snoopCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit.snoop_hit_with_fwdocr.demand_rfo.supplier_none.snoop_missCounts any other requests OCR.OTHER.L3_HIT.SNOOP_MISSocr.other.l3_hit_s.hitm_other_coreCounts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.supplier_none.any_snoopocr.pf_l2_data_rd.l3_hit.no_snoop_neededCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.supplier_none.snoop_noneocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_neededocr.pf_l3_data_rd.l3_hit_f.no_snoop_neededocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOPumask=0x8,event=0x37Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablabilityCounts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCycles DSB is delivering optimal number of UopsCounts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architectureCounts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cacheCounts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cacheperiod=100003,umask=0x20,event=0xc8Counts the number of PREFETCHNTA instructions executedperiod=10000003,umask=0x8,event=0xa4ocr.other.l3_hit.snoop_sentocr.other.l3_hit.snoop_hit_no_fwdCounts cycles where the pipeline is stalled due to serializing operationsperiod=2000003,umask=0x1,event=0Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Precise event)Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathCounts all branch instructions retired (Precise event)uops_retired.slotscmask=20,period=1000003,umask=0x14,event=0xa3br_misp_retired.cond_takenperiod=100003,umask=0x10,event=0x49period=100003,umask=0x1,event=0xb7,offcore_rsp=0x108002LM Tag Check : Miss, no data in this line. Unit: uncore_imc unc_m_tagchk.nm_wr_hitunc_cha_tor_occupancy.ia_hitumask=0xCD43FD04,event=0x35Four byte data request of the CPU : Card writing to DRAM. Unit: uncore_iio fc_mask=0x07,ch_mask=0x02,umask=0x80,event=0x84fc_mask=0x07,ch_mask=0x80,umask=0x80,event=0x83unc_iio_comp_buf_occupancy.cmpd.part5PCIe Completion Buffer Occupancy of completions with data : Part 4. Unit: uncore_iio Clockticks of the mesh to memory (M2M). Unit: uncore_m2m Counts the number of load uops retired that miss in the level 2 cache  Supports address when precise (Precise event)Counts the number of instructions retired (Precise event)Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event)TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filterCounts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM)Counts the number of cycles a core is stalled due to a store buffer being fullcycles:k / cyclesCounts the number of times a decode restriction reduces the decode throughput due to wrong instruction length predictionCounts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basisperiod=1000003,umask=0x2,event=0x73period=1000003,umask=0x4,event=0x73topdown_be_bound.store_bufferperiod=200003,umask=0xfb,event=0xc5period=200003,umask=0x7e,event=0xc5Counts the total number of machine clears including memory ordering, memory disambiguation, self-modifying code, page faults and floating point assistCounts the number Extended Page Directory Pointer Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesperiod=200003,umask=0x12,event=0xd0The number of instruction fetches that hit in the L1 ITLBevent=0x84All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmdumask=0x10,event=0x61umask=0x10,event=0x64l2_cache_req_stat.ic_access_in_l2event=0xc3umask=0x01,event=0x1cfumask=0x02,event=0x7c7fpu_pipe_assignment.dualThe number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0fpu_pipe_assignment.totalThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPSfp_num_mov_elim_scal_op.sse_mov_ops_elimevent=0x35Number of STLF hitsThe number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative eventls_tablewalker.ic_type1Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2umask=0x02,event=0x28abranch_misprediction_ratiol2_cache_accesses_from_ic_missesAll L2 Cache Missesl2_itlb_missesumask=0x01,event=0x85ex_ret_cond_mispfp_ret_sse_avx_ops.add_sub_flopsumask=0x01,event=0x43Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevelumask=0xff,event=0xaade_dis_dispatch_token_stalls1.int_sched_misc_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semanticsInstruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cacheThe number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatchMultiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventumask=0x40,event=0x44l1_data_cache_fills_allNB_HT_BUS2_BANDWIDTHEVENT_22HEVENT_4DHEVENT_68HEVENT_7BHEVENT_D9HSTREX_PASSEDMEM_ACCESS_LDBR_RETURN_SPECISB_SPECMEM_CAP_READ_TAG_SETINSTR_REFETCHINTEGER_INSNSNT_MUL_DIV_INSNSDSP_BRANCH_INSNSEXCEPTIONS_TAKENFSB_25_50_FULLIDIDSIOLDSDTLBADTHRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLESDST_INSTR_DISPATCHEDVTQ_LINE_FETCHBRANCH_LINK_STACK_MISPREDICTEDL3_DATA_CACHE_MISSESLSU_EMPTYDISPATCH_SUCCESSBUS_HIGHUOPS_COMPLETEDSTORE_UOPS_COMPLETEDCYCLES_DECODE_STALLEDINSTR_L1_CACHE_LOCKSL2_CACHE_INSTR_HITSSOFT-k8-fr-retired-taken-branches-mispredictedic-missesK8-usrgspostwrszbyteAMD_K8INTEL_ATOMmem_load_l3_miss_retired.remote_hitmRESOURCE_STALL%s, "tsc": "%jd"CoreIPCC3_Pkg_ResidencyThis event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new typesl2_rqsts.all_pfumask=0x1,period=100003,event=0xb0mem_uops_retired.split_loadsThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event)umask=0x20,period=100007,event=0xd1umask=0x4,period=100007,event=0xd3L2 cache accesses when fetching instructionsL2 cache lines filling L2Number of SIMD FP assists due to input valuesidq_uops_not_delivered.coreUops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalledThis event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
 a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
 b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); 
 c. Instruction Decode Queue (IDQ) delivers four uopsumask=0x1,period=2000003,event=0x5This event counts speculative cache-line split load uops dispatched to the L1 cacheThis event counts speculative cache line split store-address (STA) uops dispatched to the L1 cacheNumber of times a TSX line had a cache conflicttx_mem.abort_hle_store_to_elided_lockumask=0x10,period=2000003,event=0x54tx_mem.hle_elision_buffer_fullumask=0x4,period=2000003,event=0x5dNumber of times we entered an HLE region; does not count nested transactionsumask=0x4,period=2000003,event=0xc9umask=0x20,period=2000003,event=0xc9rtm_retired.aborted_misc4This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock timemove_elimination.int_not_eliminatedTaken speculative and retired indirect callsTaken speculative and retired mispredicted macro conditional branchesThis event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1umask=0x4,any=1,period=2000003,event=0xa1uops_dispatched_port.port_4umask=0x20,period=2000003,event=0xa1Resource-related stall cyclescycle_activity.cycles_no_executeumask=0x2,cmask=4,period=2000003,event=0xb1umask=0x1,period=2000003,event=0xc3Return instructions retired. (Precise Event - PEBS) (Precise event)umask=0x20,period=2000003,event=0xccumask=0x1,event=0x37umask=0x3,event=0x4unc_m_pre_count.page_missuncore powerThis event counts load misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69Store misses in all DTLB levels that cause completed page walks (1G)  Spec update: BDM69Store operations that miss the first TLB level but hit the second and do not cause page walksumask=0x1,period=100007,event=0xbdPipeline;RetireDSB;Fetch_BWInstruction_TypeIpSBranchesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0002offcore_response.corewb.supplier_none.snoop_hitmoffcore_response.corewb.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020008offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020010offcore_response.pf_l2_code_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010040offcore_response.pf_l2_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0091This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalidumask=0x1,period=2000003,cmask=4,event=0x9cumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000008offcore_response.corewb.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000010offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dramoffcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_neededoffcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C008000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C008000offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwdoffcore_response.all_data_rd.l3_miss.snoop_not_neededoffcore_response.all_rfo.supplier_none.snoop_non_dramCycles no executable uops retired (Precise Event)unc_arb_trk_occupancy.cycles_with_any_requestMiss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise (Precise event)Counts all prefetch (that bring data to LLC only) RFOs hit in the L3Counts all demand data writes (RFOs) hit in the L3l2_st.self.s_stateumask=0x72,period=200000,event=0x2el2_rqsts.self.prefetch.e_statel2_rqsts.self.prefetch.i_statel2_rqsts.self.prefetch.mesiL1 Cacheable Data ReadsModified cache lines evicted from the L1 data cacheFloating point assistsSIMD packed multiply micro-ops retiredumask=0x88,period=2000000,event=0xb3simd_comp_inst_retired.scalar_singleumask=0x2,period=200000,event=0x80umask=0x1,period=2000000,cmask=1,event=0xa9misalign_mem_ref.rmw_splitStreaming SIMD Extensions (SSE) PrefetchT0 instructions executedStreaming SIMD Extensions (SSE) PrefetchT2 instructions executedStreaming SIMD Extensions (SSE) Prefetch NTA instructions executedumask=0x80,period=200000,event=0x6Memory bus transactionsumask=0x40,period=200000,event=0x7fbr_missp_type_retired.indumask=0x2,period=2000000,event=0xdcumask=0x7,period=200000,event=0x8Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victimsLoads retired that came from DRAM (Precise event capable)  Supports address when precise (Must be precise)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000022Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredoffcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwdCounts bus lock and split lock requests that have any transaction responses from the uncore subsystemCounts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=203,event=0xcbhw_interrupts.pending_and_maskedCounts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this eventld_blocks.utlb_missCore cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counterCounts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal resultumask=0xf7,period=200003,event=0xc5br_misp_retired.ind_callRetired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise)itlb.missCounts uops retired that had a DTLB miss on load, store or either.  Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss  Supports address when precise (Must be precise)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000010Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032b7dtlb_load_misses.walk_pendingPage walk completed due to an instruction fetch in a 2M or 4M pageitlb_misses.walk_pendingNumber of instruction fetches that missed the L2 cacheIncrements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrencesCounts all prefetch (that bring data to L2) RFOs hit in the L3Randomly selected loads with latency value being above 16  Spec update: HSD76, HSD25, HSM26 (Must be precise)miss in the L3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00200offcore_response.pf_l2_code_rd.l3_miss.any_responseThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt stateThis event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issuedumask=0x4,period=2000003,event=0x87Cycles with pending memory loadsNumber of instructions retired. General Counter   - architectural event  Spec update: HSD11, HSD140Branch instructions at retirementAn external snoop hits a non-modified line in some processor coreumask=0x48,event=0x34This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB missesRetired load uops missed L2. Unknown data source excluded  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwdClean L2 cache lines evicted by L2 prefetchumask=0x8,period=100003,event=0xf2offcore_response.all_rfo.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0001Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core cachesCounts non-temporal stores(( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / cyclesLoads with latency value being above 128 (Must be precise)mem_trans_retired.precise_storeCounts LLC replacementsCycles per thread when uops are dispatched to port 5uops_dispatched_port.port_5_coreCycles stalled due to no store buffers available (not including draining form sync)Cycles with pending L2 cache miss loadsumask=0x08,event=0x34umask=0x80,period=100003,event=0x85offcore_response.pf_l2_data_rd.llc_hit.snoop_missCounts all demand code reads that miss the LLCllc_references.pcie_ns_readQPI clock ticks. Use to get percentages for QPI cycles events. Unit: uncore_qpi (unc_p_freq_band1_cycles / unc_p_clockticks) * 100.unc_p_freq_band2_transitionsevent=0xb,filter_band0=12(unc_p_freq_ge_1200mhz_cycles / unc_p_clockticks) * 100.Retired store uops that miss the STLB (Precise event)Retired load uops with locked access (Precise event)This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterizationThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventsumask=0xa,period=2000003,event=0xa2umask=0xc,event=0x1This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB missesumask=0x4,period=200003,event=0x86mem_uops_retired.l2_miss_loadsoffcore_response.any_read.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400200umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080080offcore_response.pf_l2_rfo.supplier_noneoffcore_response.demand_code_rd.l2_hit_far_tile_e_fCounts Demand cacheable data writes that accounts for any responseoffcore_response.pf_software.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004001000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00080032f7offcore_response.demand_code_rd.l2_hit_this_tile_foffcore_response.demand_rfo.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800401000offcore_response.any_pf_l2.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x01004032f7Counts L1 data HW prefetches that accounts for data responses from DRAM Faroffcore_response.bus_locks.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200200umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400100offcore_response.partial_writes.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600001umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600002umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600020offcore_response.any_pf_l2.mcdramCounts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800400Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is assertedrecycleq.st_splitsCounts any retired store that was pushed into the recycle queue for any reasonunc_m_cas_count.rdumask=0x1,period=2000000,event=0x63l1d.m_evictL1 data cache load locks in M stateL1D prefetch load lock accepted in fill bufferL1D hardware prefetch requests triggeredl1d_wb_l2.s_stateumask=0x10,period=200000,event=0xf0All L2 demand store RFOs that hit the cacheumask=0xf,period=100000,event=0x27Loads delayed with at-Retirement block codeoffcore_response.any_data.local_cacheoffcore_response.any_ifetch.llc_hit_no_other_coreOffcore requests satisfied by any cache or DRAMOffcore requests satisfied by a remote cacheOffcore request = all data, response = any cache_dramoffcore_response.demand_data.llc_hit_other_core_hitmoffcore_response.demand_data_rd.llc_hit_other_core_hitoffcore_response.demand_data_rd.local_cache_dramoffcore_response.demand_ifetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x102Offcore prefetch data requests satisfied by the LLC or local DRAMOffcore prefetch code reads satisfied by the IO, CSR, MMIO unitumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF20Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3820umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1870umask=0x8,period=200000,event=0xfdmacro_insts.fusions_decodedumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4011umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2077umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2033offcore_response.demand_data_rd.any_llc_missoffcore_response.demand_data_rd.remote_dramOffcore demand code reads satisfied by any DRAMoffcore_response.demand_rfo.remote_dramumask=0x1,period=200000,event=0x7sb_drain.anyThread responded HIT to snoopbaclear_force_iqMispredicted unconditional branches executedbr_misp_exec.direct_near_callAny Instruction Length Decoder stall cyclesinst_decoded.dec0machine_clears.mem_orderumask=0x4,period=20000,event=0xc3umask=0x1,period=200000,event=0xc7SIMD Scalar-Single Uops retired (Precise Event)inv=1,umask=0x40,period=2000000,cmask=1,event=0xb1Uops executed on port 4 (core count)Cycles Uops are not retiring (Precise Event)dtlb_load_misses.anyoffcore_response.demand_data_rd.l3_hit_s.spl_hitperiod=100003,umask=0x1f,event=0xf1period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100004offcore_response.demand_code_rd.l3_hit_e.snoop_missmem_load_l3_hit_retired.xsnp_hitoffcore_response.demand_rfo.l3_hit_m.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0040002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0040004offcore_response.demand_code_rd.l3_hit_m.snoop_hitmperiod=20011,umask=0x1,event=0xd2period=100003,umask=0x10,event=0xf4offcore_response.other.l4_hit_local_l4.spl_hitoffcore_response.demand_data_rd.l3_hit_m.any_snoopCounts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100408000period=100003,umask=0x12,event=0xd0period=2000003,umask=0x1,event=0xc7Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQperiod=2000003,umask=0x20,event=0x79icache_64b.iftag_stallRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x007C408000offcore_response.demand_data_rd.l3_miss.snoop_non_dramNumber of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writesperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C400001offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000002Counts the number of hardware interruptions received by the processorCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3cmask=10,inv=1,period=2000003,umask=0x1,event=0xc0Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECTuops_retired.retire_slots / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))SMT;TopDownL1( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branchesStores that miss the DTLB and hit the STLBCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a loadThis event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0)Any reissued load uopsCounts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheoffcore_response.any_request.l2_miss.snoop_missumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000100offcore_response.pf_l2_code_rd.l2_miss.snoop_missCounts demand and DCU prefetch instruction cacheline that have any response typeCounts the number of times a decode restriction reduced the decode throughput due to wrong instruction length predictionCounts the number of taken JCC branch instructions retired (Precise event)NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)umask=0x50,period=200003,event=0xcaThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclearsDuration of D-side page-walks in core cyclesThis event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event)Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0120COREWB & ANY_RESPONSEumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0040offcore_response.pf_llc_rfo.llc_hit.snoop_missCounts all data/code/rfo references (demand & prefetch) Counts demand data writes (RFOs) that miss the LLC and the data returned from dramoffcore_requests.anyREQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAMREQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHEREQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAMREQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIToffcore_response.pf_rfo.all_local_dram_and_remote_cache_hitREQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PREFETCH and RESPONSE = ANY_LOCATIONREQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf8ffREQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISSumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf810umask=0x1,period=20000,event=0xc5DTLB misses casued by low part of addressumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2733umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF50Counts prefetch RFOs that hit in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010122Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0080Counts prefetch RFOs that miss the L3 and the data is returned from local dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800001Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dramMemoryBW;Offcore1 - cpu_clk_unhalted.one_thread_active / ( cpu_clk_unhalted.ref_xclk_any / 2 ) if #smt_on else 0unc_m_wpq_insertsumask=0xf,event=0x2PCI Express bandwidth writing at IIO, part 3. Unit: uncore_iio umask=0x01,event=0x11Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbIPCIe Completion Buffer Inserts of completions with data: Part 2. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 1fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x83unc_iio_txn_req_of_cpu.peer_read.part2fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x84Occupancy of the IRP FAF queue. Unit: uncore_irp Number of reads in which direct to Intel UPI transactions were overridden. Unit: uncore_m2m unc_m2m_direct2upi_not_taken_dirstateMulti-socket cacheline Directory update from S to A. Unit: uncore_m2m unc_m2m_imc_writes.niunc_m2m_rxc_bl_insertsBL Egress (to CMS) Occupancy; Allunc_upi_direct_attempts.d2uumask=0x2,event=0x31unc_upi_txl_flits.non_dataperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020490This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100120offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwdoffcore_response.all_reads.l3_hit.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000407F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200122offcore_response.demand_code_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.other.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200400offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwdoffcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000120OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITMOCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwdocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITMperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000002ocr.demand_rfo.l3_miss.hit_other_core_fwdCounts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOPocr.other.l3_miss_local_dram.hitm_other_coreocr.other.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810008000ocr.pf_l1d_and_sw.l3_miss.remote_hit_forwardocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoopocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONECounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwdocr.pf_l2_rfo.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000080ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITMocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.all_data_rd.l3_miss.hit_other_core_fwdoffcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.all_reads.l3_miss.remote_hitmThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITMoffcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.other.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoopoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwdoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_noneOCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISSocr.all_pf_data_rd.l3_hit.any_snoopocr.all_pf_data_rd.l3_hit.hit_other_core_fwdOCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.all_pf_rfo.l3_hit_f.hit_other_core_fwdocr.all_pf_rfo.l3_hit_m.hit_other_core_fwdOCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_HIT_F.ANY_SNOOP  OCR.ALL_READS.L3_HIT_F.ANY_SNOOPOCR.ALL_READS.L3_HIT_M.SNOOP_NONEOCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_COREocr.all_rfo.l3_hit_m.hit_other_core_no_fwdocr.all_rfo.pmm_hit_local_pmm.snoop_noneocr.demand_code_rd.l3_hit.any_snoopCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISSCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_e.snoop_noneocr.demand_data_rd.supplier_none.hit_other_core_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit.no_snoop_neededocr.other.l3_hit.snoop_noneocr.other.l3_hit_m.no_snoop_neededocr.other.supplier_none.hit_other_core_no_fwdocr.pf_l2_data_rd.l3_hit_m.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORECounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONECounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORECounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.pf_l3_rfo.any_responseocr.pf_l3_rfo.l3_hit_s.no_snoop_neededocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoopTOR Occupancy : DRds issued by iA Cores that Missed the LLC. Unit: uncore_cha period=1000003,umask=0x4,event=0x48Counts demand requests to L2 cacheCounts retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event)Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementDecode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITECounts Unfriendly TSX abort triggered by a vzeroupper instructionocr.hwpf_l1d_and_swpf.l3_missocr.demand_code_rd.l3_missocr.hwpf_l2_rfo.any_responseocr.hwpf_l2_data_rd.l3_hit.snoop_hitmocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwdocr.demand_data_rd.l3_hit.snoop_not_neededTMA slots available for an unhalted logical processor. Fixed counter - architectural eventCounts the number of PREFETCHT1 or PREFETCHT2 instructions executedCounts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resourcesocr.demand_code_rd.l3_hit.anyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1E003C0004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1E003C0002Not taken branch instructions retired (Precise event)Counts not taken branch instructions retired (Precise event)int_misc.all_recovery_cyclesnumber of branch instructions retired that were mispredicted and taken. Non PEBS (Precise event)Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)C1_Core_ResidencyCounts writes that generate a demand reads for ownership (RFO) request and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedunc_m_hclockticksevent=0xffumask=0xC887FD01,event=0x35TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_partial_streaming_wrumask=0xC8F3FE04,event=0x35unc_iio_data_req_of_cpu.mem_write.part4unc_iio_txn_req_of_cpu.mem_read.part4fc_mask=0x04,ch_mask=0x40,umask=0x03,event=0xc2Valid Flits Received : All Non Data. Unit: uncore_upi ll Cycles in L0p. Unit: uncore_upi ll Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses a programmable general purpose performance counterunc_cha_tor_inserts.ia_miss_wcilData requested of the CPU : Card reading from DRAM. Unit: uncore_iio period=200003,umask=0x40,event=0x34topdown_fe_bound.predecodeCounts the total number of branch instructions retired for all branch types (Precise event)period=2000003,umask=0x2,event=0x4fic_fw32_missbp_snp_re_syncic_cache_inval.l2_invalidating_probeAll L2 Cache Requests (Breakdown 1 - Common). Instruction cache readsAll L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current statel2_request_g2.smc_invall2_latency.l2_cycles_waiting_on_fillsLS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requestsRetired Branch Resyncsevent=0xcaex_ret_mmx_fp_instr.mmx_instrex_div_busyremote_outbound_data_controller_1fpu_pipe_assignment.dual2Double precision multiply FLOPSThe number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bitsls_misal_accessesic_oc_mode_switch.oc_ic_mode_switchumask=0x40,event=0xafde_dis_dispatch_token_stalls0.alsq1_token_stallevent=0x2cL1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLBumask=0x07,event=0x28fop_cache_hit_miss.op_cache_hitevent=0x90Counts retired Fused InstructionsDemand Data Cache Fills by Data Source. From DRAM or IO connected in same nodeumask=0x02,event=0x44The number of 4KB misaligned (i.e., page crossing) loadsumask=0x04,event=0xabumask=0x03,event=0x44hwpmcFR_RETIRED_TAKEN_BRANCHESDTLB_REFILLL2_STORE_BUFFERABLEEVENT_02HEVENT_0EHEVENT_3CHEVENT_77HEVENT_E1HPLE_CACHE_LINE_REQ_COMPLETEDL1D_CACHE_WB_CLEANBUS_ACCESS_SHAREDBUS_ACCESS_PERIPHL2D_TLB_REFILLTAGCACHE_READ_MISSJTLB_DACCESSDMISS_CYCLESBRANCH_INSNSIPSYNCIOBINSTR_DISPATCHEDBRANCH_UNIT_STALL_CYCLESCYCLES_THREE_INSTR_DISPATCHEDLS_LM_COMPLETEDSS_SM_INSTR_COMPLETEDCYCLES_ONE_INSTR_DISPATCHEDCACHEABLE_STORE_MERGE_TO_32_BYTESSWITCHES_BETWEEN_PRIV_USERCYCLES_THREE_INSTR_COMPLETEDSNOOP_RETRIESRAQ_FULL_CYCLESL1_EXTERNAL_INTERVENTIONSDTQ_FULL_CYCLESBUS_RETRY_DUE_TO_L1_RETRYCYCLES_RUNNING_PURR_INCPMC2_OVERFLOWSTALLS_NO_CAQ_OR_COBDECORATED_LOADScount=ownerpage-missdimm-turnaroundwrite-to-read-turnaroundls_not_halted_cyckern.hwpmc.cpuidAuthenticAMD{"type": "map_out"FrontendSummaryTotal issue-pipeline slots(cstate_pkg@c3\-residency@ / msr@tsc@) * 100Demand Data Read requests that hit L2 cacheRFO requests that hit L2 cacheumask=0xe1,period=200003,event=0x24L2 code requestsumask=0xff,period=200003,event=0x24Not rejected writebacks that hit L2 cacheumask=0x1,cmask=1,period=2000003,event=0x48umask=0x1,period=2000003,event=0x60offcore_requests_outstanding.all_data_rdCacheable and noncachaeble code read requestsumask=0x12,period=100003,event=0xd0mem_load_uops_retired.l2_hitThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)mem_load_uops_l3_miss_retired.remote_hitml2_trans.l2_fillumask=0x20,period=200003,event=0xf0umask=0x80,period=200003,event=0xf0umask=0x8,period=100003,event=0xcaumask=0x10,period=100003,event=0xcaThis event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist interventionumask=0x1e,cmask=1,period=100003,event=0xcaThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQNumber of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetchesumask=0x1,cmask=3,period=2000003,event=0x9cumask=0x2,period=2000003,event=0xabCounts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abortThis event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:
1. memory disambiguation,
2. external snoop, or
3. cross SMT-HW-thread snoop (stores) hitting load bufferhle_retired.aborted_misc1rtm_retired.aborted_misc5mem_trans_retired.load_latency_gt_128umask=0x8,period=100003,event=0x3umask=0x0,any=1,period=2000003,event=0x3cNot software-prefetch load dispatches that hit FB allocated for software prefetchNumber of SIMD Move Elimination candidate uops that were eliminatedThis event counts cycles during which the reservation station (RS) is empty for the thread.
Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issuesumask=0x1,period=2000003,event=0x87umask=0xa0,period=200003,event=0x88This event counts both taken and not taken speculative and retired branch instructionsThis event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5umask=0x1,period=2000003,event=0xa8machine_clears.cyclesedge=1,umask=0x1,cmask=1,period=100003,event=0xc3This event counts the number of mispredicted ret instructions retired.(Precise Event)umask=0x3,event=0x35,filter_opc=0x187unc_h_requests.writes_remoteunc_m_power_channel_ppdumask=0x1,event=0x2event=0x6freq_max_os_cycles %Load misses that miss the  DTLB and hit the STLB (4K)umask=0x8,period=100003,event=0x49umask=0x20,period=100003,event=0x49Store misses that miss the  DTLB and hit the STLB (4K)Misses at all ITLB levels that cause page walks  Spec update: BDM69umask=0x14,period=2000003,event=0xbcNumber of ITLB page walker hits in the L2  Spec update: BDM69, BDM98RetiringInstructions per Branch (lower number means higher occurance rate)inst_retired.any / br_inst_retired.near_call64 * longest_lat_cache.miss / 1000000000 / duration_timeoffcore_response.demand_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0001offcore_response.demand_code_rd.any_responseoffcore_response.demand_code_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020008offcore_response.pf_l2_data_rd.supplier_none.snoop_noneoffcore_response.pf_l2_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020080offcore_response.pf_l3_data_rd.supplier_none.snoop_hitmoffcore_response.pf_l3_rfo.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80028000Counts all prefetch code reads have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020240offcore_response.all_rfo.l3_hit.snoop_noneAny input SSE* FP Assist -   (Precise Event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000040offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_neededoffcore_response.pf_l3_code_rd.l3_miss.snoop_not_neededoffcore_response.other.l3_miss_local_dram.snoop_missoffcore_response.other.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000091offcore_response.all_rfo.l3_miss_local_dram.snoop_not_neededoffcore_response.all_rfo.l3_miss.snoop_not_neededUnit: uncore_cbox L3 Lookup any request that access cache and found line in M-stateUnit: uncore_arb Number of Core coherent Data Read entries allocated in DirectData modeNumber of Writes allocated - any write transactions: full/partials writes and evictionsThis event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches  Supports address when precise (Precise event)This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event)offcore_response.all_reads.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC00091This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight  Supports address when precise (Precise event)l2_dbus_busy.selfumask=0x42,period=200000,event=0x2cl2_ld_ifetch.self.m_stateumask=0x48,period=200000,event=0x2eumask=0x54,period=200000,event=0x2eL2 cache demand requests from this coreumask=0x7f,period=200000,event=0x30simd_uops_exec.arRetired Streaming SIMD Extensions 2 (SSE2) vector instructionsumask=0x8f,period=200000,event=0x5umask=0x8a,period=200000,event=0x5Any Software prefetchumask=0xe0,period=200000,event=0x65Explicit writeback bus transactionsbus_trans_ifetch.selfbus_trans_pwr.selfIO bus transactionsumask=0xb,period=200000,event=0x77store_forwards.goodumask=0x7f,period=200000,event=0x3All indirect calls, including both register and memory indirectMispredicted return branchesuops_retired.anyumask=0x2,period=200000,event=0xc4umask=0x4,period=2000000,event=0xc4Micro-op reissues on a store-load collisionDuration of I-Side page walksumask=0x41,period=200003,event=0xd0umask=0x10,period=200003,event=0xd1offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_neededCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400002000offcore_response.sw_prefetch.l2_miss.anyCounts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of times the prediction (from the predecode cache) for instruction length is incorrectCounts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystemCounts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts bus lock and split lock requests hit the L2 cacheoffcore_response.full_streaming_stores.any_responseoffcore_response.sw_prefetch.any_responseCounts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystemCycles the code-fetch stalls and an ITLB miss is outstandingInstructions retired (Fixed event) (Must be precise)Page walk completed due to a demand load to a 2M or 4M pagePage walks outstanding due to walking the EPT every cycleumask=0x2,period=2000003,event=0x85All requests to L2 cache  Spec update: HSD78Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwdCounts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedInstruction Decode Queue (IDQ) empty cycles  Spec update: HSD135Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE  Spec update: HSD135Number of times an HLE execution startedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00010This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions  Spec update: HSD140, HSD143Cycles which a uop is dispatched on port 4 in this threadNumber of uops delivered by the LSDUnit: uncore_cbox An external snoop misses in some processor coreA cross-core snoop resulted from L3 Eviction which hits a modified line in some processor coreumask=0x01,event=0x83Number of DTLB page walker hits in the L1+FBumask=0x84,period=2000003,event=0xbcpage_walker_loads.ept_itlb_memoryumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00020umask=0x8,period=200003,event=0x24Retired store uops that miss the STLB. (Precise Event)l2_lines_out.pf_dirtyCounts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts 256-bit packed single-precision floating-point instructionsDSB Fill encountered > 3 DSB linesunc_cbo_xsnp_response.inval_mFilter on processor core initiated cacheable read requestsUnit: uncore_arb Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0090Counts all data/code/rfo reads (demand & prefetch) that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00001offcore_response.demand_data_rd.llc_miss.remote_dramCounts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from thereStreaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full. Unit: uncore_cbox Read requests to home agent. Unit: uncore_ha unc_q_rxl0p_power_cyclesevent=0x10freq_band0_cycles %unc_p_freq_band1_cyclesL1D data cache lines in M state evicted due to replacementThis event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excludedumask=0x40,period=2000003,event=0x59Resource stalls out of order resources fullOccupancy counter for memory read queue. Unit: uncore_imc mem_uops_retired.l2_hit_loadsCounts all the store micro-ops retiredoffcore_response.any_read.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800082000offcore_response.uc_code_reads.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080020umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080002Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000022umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010008000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00100032f7Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateCounts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeCounts any Read request  that accounts for data responses from DRAM Faroffcore_response.any_code_rd.mcdram_nearoffcore_response.pf_software.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000200offcore_response.partial_reads.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400001Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event)This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector dividesrecycleq.ld_block_std_notreadyumask=0x20,period=200003,event=0x3umask=0x2,period=2000000,event=0x63l1d.replumask=0x1,period=2000000,event=0x53l1d_cache_st.m_stateL2 RFO requestsl2_transactions.rfoumask=0x40,period=100000,event=0xb0store_blocks.at_retumask=0x8,period=200000,event=0x6mem_inst_retired.latency_above_threshold_32All offcore data readsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1844umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3844umask=0x1,period=100000,event=0xb7,offcore_rsp=0x222offcore_response.any_rfo.remote_cacheOffcore demand code reads that HIT in a remote cacheoffcore_response.demand_ifetch.remote_cache_hitmOffcore demand RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_rfo.remote_cacheoffcore_response.demand_rfo.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F80offcore_response.other.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1030offcore_response.pf_data_rd.remote_cache_hitmoffcore_response.pf_ifetch.any_cache_dramOffcore prefetch code reads satisfied by the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x840umask=0x1,period=100000,event=0xb7,offcore_rsp=0x220offcore_response.prefetch.any_cache_dramAll offcore prefetch requestsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x170Offcore prefetch requests satisfied by a remote cache or remote DRAMX87 Floating point assists (Precise Event)fp_assist.outputfp_comp_ops_exe.sse_single_precisionsimd_int_128.packed_shiftumask=0x20,period=200000,event=0xfdumask=0x1,period=2000000,event=0xa6umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF822Offcore RFO requests that missed the LLCoffcore_response.data_ifetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6003umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF804umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF810umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF870baclear.bad_targetBranch instructions executedbr_inst_exec.condbr_misp_exec.non_callsMispredicted taken branches executedumask=0x1,period=2000000,event=0x17umask=0x2,period=200000,event=0xc7umask=0x10,period=200000,event=0xc7uops_executed.port2_coreumask=0x80,any=1,period=2000000,event=0xb1inv=1,umask=0x1,any=1,period=2000000,cmask=1,event=0xeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC01C0004offcore_response.demand_code_rd.l3_hit_e.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000400001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400004offcore_response.demand_rfo.l3_hit_m.snoop_missCounts the number of lines that have been hardware prefetched but not used and now evicted by L2 cacheoffcore_response.demand_rfo.l3_hit_s.any_snoopoffcore_response.demand_rfo.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100001offcore_response.demand_rfo.l4_hit_local_l4.any_snoopoffcore_response.demand_rfo.l3_hit_s.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100002Retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event)Counts retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event)offcore_response.demand_data_rd.l3_hit_m.snoop_noneoffcore_response.other.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000048000offcore_response.other.l4_hit_local_l4.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801C8000offcore_response.demand_rfo.l3_hit_s.snoop_noneRetired instructions after front-end starvation of at least 1 cycle (Must be precise)frontend_retired.latency_ge_256Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)offcore_response.demand_code_rd.l3_miss.spl_hithle_retired.aborted_timerCounts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)offcore_response.other.l3_miss.spl_hitoffcore_response.other.l3_miss.snoop_non_dramperiod=20011,umask=0x1,event=0xcd,ldlat=0x10period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0044000004cmask=2,period=2000003,umask=0x1,event=0xb1period=2000003,umask=0x2,event=0xa1period=400009,umask=0x20,event=0xc4Counts the number of macro-fused uops retired. (non precise)Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions1000 * mem_load_retired.l2_miss / inst_retired.anyCounts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008008umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000010umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000004Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative countALL_BRANCHES counts the number of any branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocationCounts the number of cycles when no uops are allocated for any reasonRetired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event)Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event)offcore_response.all_pf_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0002offcore_response.pf_l2_rfo.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0020Counts all prefetch (that bring data to LLC only) data reads that hit in the LLCCounts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedREQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSECounts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dramumask=0x8,period=2000000,cmask=1,event=0x60umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5008REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3011umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3033umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf801REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = OTHER and RESPONSE = REMOTE_DRAMREQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = PF_RFO and RESPONSE = ANY_LLC_MISSdtlb_load_misses.walk_cyclesdtlb_misses.pde_missITLB miss large page walksOffcore uncached memory accessesinv=1,umask=0x1f,period=2000000,cmask=1,edge=1,event=0xb1Retired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise (Precise event)Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0001offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_coreoffcore_response.pf_l2_data_rd.l3_hit.no_snoop_neededOFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0080Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementoffcore_response.all_data_rd.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00120offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdoffcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forwardoffcore_response.pf_l2_data_rd.l3_miss.remote_hit_forwardCounts all prefetch (that bring data to LLC only) data reads that miss in the L3offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800080offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd1000 * l2_lines_out.silent / inst_retired.any( unc_iio_data_req_of_cpu.mem_write.part0 + unc_iio_data_req_of_cpu.mem_write.part1 + unc_iio_data_req_of_cpu.mem_write.part2 + unc_iio_data_req_of_cpu.mem_write.part3 ) * 4 / 1000000000 / duration_timeAll DRAM Read CAS Commands issued (does not include underfills). Unit: uncore_imc event=0x20umask=0x02,event=0x53unc_cha_llc_victims.total_munc_cha_requests.invitoe_localLocal requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha unc_cha_sf_eviction.e_stateunc_cha_snoop_resp.rspiPeer to peer read request for 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part2Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit. Unit: uncore_iio Inbound read requests received by the IRP and inserted into the FAF queue. Unit: uncore_irp Traffic in which the M2M to iMC Bypass was not taken. Unit: uncore_m2m Counts when messages were sent direct to core (bypassing the CHA)Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new stateunc_m2m_imc_reads.allunc_m2m_rxc_ad_insertsunc_m2m_rxc_bl_occupancyunc_m2m_txc_ad_occupancyunc_upi_direct_attempts.d2cCycles the Rx of the Intel UPI is in L0p power mode. Unit: uncore_upi ll umask=0x0F,event=0x3Valid data FLITs received from any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unitThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020491offcore_response.all_pf_data_rd.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F801007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.all_rfo.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800088000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_e.no_snoop_neededoffcore_response.pf_l2_rfo.l3_hit_m.any_snoopoffcore_response.pf_l2_rfo.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040100offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400100Average 3DXP Memory Bandwidth Use for reads [GB / sec]Average 3DXP Memory Bandwidth Use for Writes [GB / sec]OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoopocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_coreocr.all_rfo.l3_miss.remote_hit_forwardOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_rfo.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000004Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_COREocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwdocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l2_data_rd.l3_miss_local_dram.snoop_missocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000080This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwdoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_coreoffcore_response.all_reads.l3_miss.hitm_other_coreoffcore_response.all_reads.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwdoffcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.pf_l1d_and_sw.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_miss.no_snoop_neededocr.all_data_rd.l3_hit.any_snoopocr.all_pf_data_rd.l3_hit_f.snoop_missocr.all_pf_data_rd.l3_hit_m.no_snoop_neededocr.all_pf_rfo.l3_hit_e.hit_other_core_fwdOCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONEocr.all_reads.l3_hit_f.any_snoopOCR.ALL_READS.L3_HIT_M.ANY_SNOOP  OCR.ALL_READS.L3_HIT_M.ANY_SNOOPOCR.ALL_READS.L3_HIT_S.ANY_SNOOP  OCR.ALL_READS.L3_HIT_S.ANY_SNOOPocr.all_reads.l3_hit_s.snoop_missOCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_rfo.l3_hit.hit_other_core_fwdocr.all_rfo.l3_hit.no_snoop_neededocr.all_rfo.l3_hit.snoop_noneocr.all_rfo.l3_hit_f.snoop_noneocr.demand_code_rd.l3_hit_e.no_snoop_neededocr.demand_data_rd.l3_hit.snoop_hit_with_fwdocr.demand_data_rd.l3_hit_f.no_snoop_neededocr.demand_data_rd.l3_hit_m.hitm_other_coreocr.demand_data_rd.supplier_none.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORECounts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDCounts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOPocr.other.l3_hit_e.snoop_missCounts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWDocr.other.supplier_none.snoop_missocr.pf_l1d_and_sw.l3_hit_e.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONECounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOPocr.pf_l2_data_rd.supplier_none.hit_other_core_fwdocr.pf_l2_rfo.l3_hit.any_snoopocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwdocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwdocr.pf_l3_data_rd.l3_hit_s.any_snoopocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOPocr.pf_l3_rfo.supplier_none.hit_other_core_fwdocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwdunc_m_pmm_rpq_insertsumask=0x20,event=0x38Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cyclecmask=1,edge=1,period=100003,umask=0x2,event=0xabRetired instructions after front-end starvation of at least 1 cycle (Precise event)ocr.demand_data_rd.l3_missSpeculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writesCounts the number of times an HLE execution aborted due to unfriendly events (such as interrupts)period=100003,umask=0x2,event=0xc8Counts demand instruction fetches and L1 instruction cache prefetches that have any type of responseCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of responseTMA slots wasted due to incorrect speculation by branch mispredictionsNumber of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch mispredictionCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredocr.demand_code_rd.l3_hit.snoop_hitmperiod=50021,umask=0x2,event=0xc5Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear eventperiod=1000003,umask=0x1,event=0x5eCounts both direct and indirect near call instructions retired (Precise event)int_misc.uop_droppingperiod=1000003,umask=0x10,event=0xduops_dispatched.port_7_8Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page faultumask=0x01,event=0x10umask=0x02,event=0x10unc_cha_tor_occupancy.ia_miss_rfoTOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha umask=0xC8170601,event=0x35Number Transactions requested by the CPU : Core writing to Card's MMIO space. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part6fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0xc1PCIe Completion Buffer Occupancy of completions with data : Part 7. Unit: uncore_iio Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cacheCounts the number of unhalted reference clock cycles at TSC frequencyperiod=2000003,event=0xcdunc_cha_tor_inserts.ia_miss_drd_optCounts the number of cacheable memory requests that access the LLC. Counts on a per core basismem_bound_stalls.load_dram_hitCounts the number of cycles a core is stalled due to a demand load which hit in the L2 cacheCounts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the dividerCounts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)period=1000003,umask=0x10,event=0x74Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return (Precise event)Counts the number of page walks completed due to load DTLB misses to a 4K pageCounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycleCounts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk)l2_request_g1.rd_blk_lumask=0x04,event=0x61Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types)event=0xc7Div Op Countumask=0x10,event=0x3Number of SSE Move Ops eliminatedThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminatedumask=0x01,event=0x29umask=0xdf,event=0x78umask=0x0e,event=0xeumask=0x01,event=0x94bp_l1_tlb_miss_l2_tlb_miss.if2mfp_ret_sse_avx_ops.mult_flopsls_locks.non_spec_lockls_refills_from_sys.ls_mabresp_rmt_dramAll TLB FlushesCycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stallumask=0x1f,event=0x18eumask=0x07,event=0x18eumask=0x03,event=0x28fumask=0x01,event=0x44Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHWHardware Prefetch Data Cache Fills by Data Source. From Local L2 to the coreall_data_cache_accessesL1 Data Cache Fills: From External CCX CacheLS_LOCKED_OPERATIONFR_RETIRED_FAR_CONTROL_TRANSFERSFR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIREFR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULLL1_DCACHE_REFILLL2_CACHE_WBMEM_REPLAY_EVTL1_ICACHE_HASH_MISSL1_CACHE_ACCESS_NOCP15EVENT_36HEVENT_37HEVENT_41HEVENT_5CHEVENT_7DHEVENT_9DHEVENT_B2HEVENT_B3HEVENT_BEHEVENT_D6HEVENT_F4HL2D_CACHE_REFILL_LDDCACHE_WRITE_MISSL2CACHE_WRITE_HITMEM_DWORD_WRITENOP_COMPLETEDWBB_FULL_PIPELINE_STALLSL2_CACHE_ACCESSESSTORE_INSNSOCP_READ_REQUESTSOCP_READ_CACHEABLE_REQUESTSFSB_LESS_25_FULLWBUFTRIU2_INSTR_COMPLETEDL1_DATA_SNOOP_HIT_CASTOUTL1_DATA_TOUCH_HITDTLB_MISSESL1_DATA_CACHE_OP_HITVT2_FETCHESIU1_INSTR_COMPLETEDL2_INSTR_CACHE_MISSESWAQ_FULL_CYCLESEXTERNAL_SNOOP_RETRYL2_LINEFILL_BUFFERSTASH_L1_HITSINSTR_LFB_WENT_HIGH_PRIORITYSNOOP_THROTTLING_TURNED_ONk8-fr-retired-taken-branchesk8-fr-taken-hardware-interruptsadd-pipe-junk-opspostwrszdwordINTEL_NEHALEM_EXINTEL_HASWELL_XEONpmclog_readunknown eventevent: %s
LLC-REFERENCEfrontend_retired.l1i_missregex '%s' failed to compile, ignoring
l3_slice_maskv13HygonGenuine-24-00CORE_CLKSl1d_pend_miss.pendingThis event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)  Spec update: BDM76This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION)Demand and prefetch data readsRetired load uops with locked access. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM35 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)mem_load_uops_l3_hit_retired.xsnp_hitmRetired load uop whose Data Source was: forwarded from remote cache (Precise Event)  Supports address when precise.  Spec update: BDE70umask=0x1,period=200003,event=0xf0This event counts L2 writebacks that access L2 cacheumask=0x10,period=100003,event=0xf4Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.doubleCycles with any input/output SSE or FP assistidq.all_dsb_cycles_any_uopsNumber of times RTM commit succeededNumber of times the TSX watchdog signaled an RTM abortNumber of times a disallowed operation caused an RTM abortLoads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)edge=1,umask=0x1,cmask=1,period=100007,event=0x5carith.fpu_div_activebr_misp_exec.taken_conditionalCycles per core when uops are dispatched to port 2Cycles per thread when uops are executed in port 4uops_executed_port.port_4cycle_activity.stalls_totalCycles 4 Uops delivered by the LSD, but didn't come from the decoderThis is a precise version (that is, uses PEBS) of the event that counts instructions retired  Spec update: BDM11, BDM55 (Must be precise)umask=0x1f,period=100003,event=0xe6(unc_p_freq_max_os_cycles / unc_p_clockticks) * 100.event=0x5dtlb_store_misses.miss_causes_a_walkThis event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.stlb_hitThis event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific)Backend_BoundBranches;PGOFLOPSoffcore_response.demand_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010004offcore_response.demand_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020010offcore_response.pf_l2_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020100offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0120offcore_response.all_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dramoffcore_response.corewb.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020010offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000020offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dramoffcore_response.pf_l3_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000080offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoopoffcore_response.all_pf_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000091umask=0x2,period=2000003,cmask=2,event=0xa3umask=0x21,event=0x34Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-stateEach cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficNumber of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etcThis event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: BDM100 (Precise event)offcore_response.pf_llc_rfo.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC007F7offcore_response.all_data_rd.llc_miss.local_dramoffcore_response.demand_rfo.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00002This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)Cycles the L2 cache data bus is busyl2_lines_out.self.anyl2_m_lines_out.self.prefetchumask=0x52,period=200000,event=0x29umask=0x42,period=200000,event=0x2aumask=0x4f,period=200000,event=0x2aumask=0x41,period=200000,event=0x2bumask=0x42,period=200000,event=0x2bl2_rqsts.self.demand.m_statel2_reject_busq.self.demand.i_statel2_reject_busq.self.prefetch.e_stateumask=0x81,period=2000000,event=0x10simd_uop_type_exec.logical.arSIMD packed logical micro-ops retiredumask=0x0,period=2000000,event=0xceumask=0x92,period=200000,event=0x5Streaming SIMD Extensions (SSE) PrefetchT1 instructions executedprefetch.prefetchntabus_bnr_drv.this_agentbus_trans_io.selfbus_trans_any.all_agentsumask=0x11,period=200000,event=0x89umask=0xf,period=2000000,event=0xc4reissue.overlap_storeumask=0x6,period=200000,event=0x8Duration of D-side only page walksL1 Cache evictions for dirty dataumask=0x2,period=200003,event=0xd1Load uops retired that missed L1 data cache (Precise event capable)  Supports address when precise (Must be precise)Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003010offcore_response.any_request.l2_miss.hitm_other_coreCounts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044800Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededoffcore_response.partial_writes.l2_miss.anyoffcore_response.pf_l2_rfo.l2_miss.hitm_other_coreCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000008umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000001umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000001Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x2,period=200003,event=0x3Duration of I-side pagewalks in cyclesumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010004Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor moduleumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000020Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.outstandingCounts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Demand data read requests that missed L2, no rejects  Spec update: HSD78Retired load uops with L1 cache hits as data sources  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)Retired load uops which data sources were HitM responses from shared L3  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xd3This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Spec update: HSD74, HSD29, HSD25, HSM30.  Supports address when preciseoffcore_response.all_data_rd.l3_hit.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads miss in the L3Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)Stall cycles because IQ is fullCycles per core when uops are executed in port 6Counts the number of far branch instructions retired (Precise event)L3 Lookup write request that access cache and found line in I-stateUnit: uncore_cbox L3 Lookup external snoop request that access cache and found line in E or S-stateNumber of ITLB page walker hits in the L1+FBumask=0x1,period=100003,event=0xbdRetired store uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.llc_hit.any_responseNumber of SIMD FP assists due to output valuesNot rejected writebacks from L1D to L2 cache lines in E stateOffcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cyclesRetired load uops with L1 cache hits as data sources (Precise event)offcore_response.all_data_rd.llc_hit.no_snoop_neededoffcore_response.all_reads.any_responseUnit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to external snoop requestumask=0x80,event=0x22unc_cbo_cache_lookup.write_filterUnit: uncore_cbox Filter on external snoop requestsFilter on external snoop requestsCycles weighted by number of requests pending in Coherency Trackerumask=0xc,period=100007,event=0xd3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0091Counts prefetch (that bring data to LLC only) data reads that miss in the LLCllc_references.itom_writeumask=0x2A,event=0x36unc_c_tor_occupancy.miss_remoteCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band3_cycles / unc_p_clockticks) * 100.event=0xc,edge=1This event counts the number of load uops retired (Precise event)umask=0x5,period=100003,cmask=1,event=0xbfIncrements the number of flags-merge uops in flight each cycleMispredicted not taken branch instructions retired (Precise event)Counts the number of load micro-ops retired that hit in the L2  Supports address when precise (Precise event)This event counts the number of store micro-ops retiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x08004032f7Counts any request that accounts for any responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800401000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400400Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400100offcore_response.pf_l2_code_rd.outstandingoffcore_response.demand_rfo.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400002offcore_response.pf_l2_rfo.l2_hit_this_tile_mCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_rfo.l2_hit_this_tile_eoffcore_response.any_rfo.l2_hit_this_tile_eoffcore_response.demand_rfo.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000022offcore_response.bus_locks.l2_hit_this_tile_fCounts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180070umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400080Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400022umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101002000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200400Counts Bus locks and split lock requests that accounts for data responses from DRAM Faroffcore_response.pf_l2_rfo.mcdram_farCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Localoffcore_response.demand_code_rd.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800040This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrtumask=0x1,period=2000000,event=0x43umask=0x8,period=100000,event=0xf2l2_rqsts.ld_hitl2_write.rfo.m_stateLoad instructions retired IO (Precise Event)Memory instructions retired above 32 clocks (Precise Event)Memory instructions retired above 512 clocks (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1811offcore_response.any_request.any_locationoffcore_response.any_request.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8022offcore_response.corewb.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x808Offcore code or data read requests satisfied by the LLC and not found in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x877umask=0x1,period=100000,event=0xb7,offcore_rsp=0x833offcore_response.demand_data.remote_cache_hitOffcore demand data reads satisfied by the LLC and not found in a sibling coreoffcore_response.demand_data_rd.local_cacheOffcore demand data reads satisfied by a remote cacheOffcore demand code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_data_rd.any_cache_dramOffcore prefetch code reads satisfied by the LLC and not found in a sibling coreoffcore_response.prefetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1070fp_assist.inputsimd_int_128.packed_mpysimd_int_64.unpacktwo_uop_insts_decodedumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6044offcore_response.any_ifetch.any_llc_missoffcore_response.any_request.any_dramoffcore_response.corewb.any_llc_missoffcore_response.prefetch.any_dramOffcore prefetch requests satisfied by any DRAMumask=0x1,period=2000000,event=0xe5Branch prediction unit missed call or returnROB read port stalls cyclesumask=0x1,period=200000,event=0x88umask=0x10,period=20000,event=0x88umask=0x30,period=2000,event=0x89Mispredicted return branches executedumask=0x2,period=2000,event=0xc5inst_queue_write_cyclesCycles when uops were delivered by the LSDinv=1,umask=0x1,period=2000000,cmask=1,event=0xa8umask=0x1,period=2000000,event=0xa2umask=0x2,period=2000000,cmask=1,event=0xd1umask=0x2,period=2000000,event=0xb1Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040020001period=100003,umask=0x41,event=0x2eperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200408000offcore_response.demand_data_rd.l4_hit_local_l4.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0020001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001C0004offcore_response.demand_rfo.supplier_none.any_snoopoffcore_response.demand_rfo.l3_hit_m.snoop_noneCounts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request typeRetired load instructions that split across a cacheline boundary  Supports address when precise (Precise event)Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementcmask=1,period=100003,umask=0x1e,event=0xcaRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event)offcore_response.other.l3_hit_e.snoop_non_dramcycle_activity.cycles_l3_missperiod=2000003,umask=0x2,event=0x5dUnfriendly TSX abort triggered by a vzeroupper instructionperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C408000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2004000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFC400001rtm_retired.aborted_unfriendlyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2004008000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFC400004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2004000001offcore_response.other.l3_hit_s.snoop_non_dramExecution stalls while L3 cache miss demand load is outstandinghle_retired.aborted_eventsperiod=2000003,event=0x3cCore crystal clock cycles when at least one thread on the physical core is unhaltedCounts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunkCounts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issuesIpLoadperiod=2000003,umask=0x10,event=0x8Instruction fetch requests that miss the ITLB and hit the STLBperiod=100003,umask=0x4,event=0x85Loads missed UTLBThis event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0240offcore_response.pf_llc_code_rd.llc_hit.snoop_missoffcore_response.pf_llc_rfo.llc_hit.hitm_other_coreCounts all demand data reads Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dramoffcore_response.demand_ifetch.llc_miss_local.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400040This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f44offcore_response.any_ifetch.local_dram_and_remote_cache_hitoffcore_response.any_request.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0xffffoffcore_response.corewb.local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f01REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8050REQUEST = PF_DATA and RESPONSE = LOCAL_CACHEREQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f20REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAMMisaligned store referencesREQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4050snoopq_requests_outstanding.invalidateOutstanding snoop invalidate requestsDTLB load miss large page walksumask=0x10,period=2000000,event=0x4fumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2711umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5802umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5880Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0002Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00491offcore_response.demand_data_rd.l3_miss.remote_hit_forwardCounts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800010offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwdCore cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedulecore_power.throttleumask=0x4,event=0x4read requests from home agent. Unit: uncore_cha 4Bytesfc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x83Normal priority reads issued to the memory controller from the CHA. Unit: uncore_cha Lines Victimized; Lines in E state. Unit: uncore_cha RspIFwd Snoop Responses Received. Unit: uncore_cha umask=0x08,event=0x5cCounts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownershipunc_iio_data_req_by_cpu.mem_write.part3Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_read.part2unc_iio_txn_req_of_cpu.mem_read.part0fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x84Multi-socket cacheline Directory lookups (any state found). Unit: uncore_m2m umask=0x20,event=0x2eunc_m2m_txc_ad_insertsBL Egress (to CMS) Allocations; All. Unit: uncore_m2m umask=0x1,event=0x31unc_upi_txl_flits.all_nullThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_f.hit_other_core_fwdoffcore_response.all_data_rd.l3_hit_f.snoop_noneoffcore_response.all_data_rd.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040491This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_f.snoop_noneoffcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_m.hitm_other_coreoffcore_response.all_pf_rfo.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C07F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C07F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000807F7offcore_response.all_reads.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000407F7offcore_response.all_reads.supplier_none.snoop_noneoffcore_response.all_rfo.l3_hit.hit_other_core_fwdoffcore_response.all_rfo.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100122This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040004offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020001This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100002offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONEoffcore_response.other.l3_hit.hit_other_core_no_fwdoffcore_response.other.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080400offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_coreoffcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwdoffcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_coreoffcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_neededoffcore_response.pf_l3_data_rd.l3_hit_f.snoop_missoffcore_response.pf_l3_data_rd.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020080This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000491ocr.all_pf_data_rd.l3_miss.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDOCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_COREOCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C0007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C0007F7ocr.all_reads.l3_miss.no_snoop_neededOCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONEocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwdOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.demand_data_rd.l3_miss.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC08000ocr.pf_l1d_and_sw.l3_miss.remote_hitmCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l2_data_rd.l3_miss.no_snoop_neededCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000020ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwdocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000100ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOPoffcore_response.all_pf_rfo.l3_miss.no_snoop_neededoffcore_response.all_reads.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.other.l3_miss.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_neededoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdOCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEOCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDOCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISSocr.all_pf_data_rd.l3_hit_f.snoop_noneOCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_COREOCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwdOCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDOCR.ALL_READS.ANY_RESPONSE have any response typeOCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOPocr.all_reads.l3_hit.hitm_other_coreOCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_COREocr.all_reads.l3_hit_m.any_snoopOCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWDOCR.ALL_READS.L3_HIT_S.SNOOP_NONEOCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit.snoop_missOCR.ALL_RFO.L3_HIT_E.SNOOP_NONEocr.all_rfo.l3_hit_m.snoop_missocr.all_rfo.l3_hit_s.snoop_missocr.all_rfo.supplier_none.snoop_noneCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_s.hit_other_core_fwdocr.demand_code_rd.supplier_none.hit_other_core_no_fwdocr.demand_code_rd.supplier_none.snoop_noneocr.demand_data_rd.l3_hit_e.hit_other_core_fwdocr.demand_data_rd.l3_hit_m.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORECounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORECounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONEocr.demand_rfo.l3_hit_e.hitm_other_coreocr.demand_rfo.l3_hit_f.hit_other_core_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOPCounts any other requests  OCR.OTHER.L3_HIT_S.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOPocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoopocr.pf_l3_rfo.l3_hit.hitm_other_coreocr.pf_l3_rfo.l3_hit_s.snoop_none6000000000nsumask=0x1,event=0xd3unc_cha_tor_inserts.ia_miss_drdcmask=1,period=1000003,umask=0x4,event=0x60period=100007,umask=0x1,event=0xc6,frontend=0x508006period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00001Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writesCounts the number of times we entered an RTM region. Does not count nested transactionsCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0400topdown.br_mispredict_slotsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010800ocr.hwpf_l2_rfo.local_dramCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or notCounts demand data reads that hit a cacheline in the L3 where a snoop was sent or notperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0800topdown.slots_pCounts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codesNumber of uops executed on port 6Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL productsNumber of uops executed on port 7 and 8Number of page walks outstanding for a store in the PMH each cycleCounts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycleOCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDAll DRAM write CAS commands issued. Unit: uncore_imc umask=0x3f,event=0x4PMM Read Pending Queue Occupancy. Unit: uncore_imc umask=0xC001FE01,event=0x35umask=0xC88FFE01,event=0x35unc_cha_tor_inserts.ia_miss_rfo_prefumask=0xCC43FD04,event=0x35unc_cha_tor_inserts.ia_miss_rfo_localumask=0xC8077E01,event=0x35TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC. Unit: uncore_cha umask=0xC8F3FD04,event=0x35umask=0xC8F3FF04,event=0x36fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0xc0unc_iio_data_req_by_cpu.mem_read.part7fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0x84PCIe Completion Buffer Inserts of completions with data: Part 4. Unit: uncore_iio unc_iio_comp_buf_occupancy.cmpd.part7umask=0x01,event=0x2dumask=0x1c,event=0x2umask=0xC827FE01,event=0x35Clockticks of the mesh to PCI (M2P)Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basisperiod=200003,umask=0x2,event=0x34Counts the number of requests to the instruction cache for one or more bytes of a cache lineperiod=200003,umask=0x2,event=0x80c0_stalls.load_llc_hitCounts the total number of issue slots every cycle that were not consumed by the backend due to backend stallstopdown_fe_bound.branch_detectperiod=200003,umask=0xf7,event=0xc5Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counterCounts the total number of instructions retired (Precise event)umask=0x80,event=0x60umask=0x01,event=0x60l2_wcb_req.wcb_writeThe number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interruptsThe number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch predictionumask=0x04,event=0xcbumask=0x38,event=0x87fp_sched_emptyfp_ret_sse_avx_ops.sp_mult_add_flopsNumber of SSE Move Opsls_mab_alloc.loadsumask=0x20,event=0x45umask=0x04,event=0x46OC Mode Switch. OC to IC mode switchumask=0x01,event=0xafumask=0x06,event=0x64L1 Instruction Cache (32B) Fetch Miss Ratiodram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8ls_hw_pf_dc_fill.ls_mabresp_lcl_l2ic_tag_hit_miss.instruction_cache_missInstruction Cache (32B) Fetch Miss RatioIC_REFILL_FROM_SYSTEMFR_RETIRED_X86_INSTRUCTIONSFR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLESNB_HT_BUS1_BANDWIDTHPC_IMM_BRANCHINSTR_EXECUTEDCYCLES_NO_INSTRUCTIONEVENT_3AHEVENT_66HEVENT_73HEVENT_A0HEVENT_C3HEVENT_C4HEVENT_CCHEVENT_D2HEVENT_F8HINSTR_MICRO_TLB_MISS_STALLL2D_CACHE_ALLOCATEICACHE_READ_MISSDCACHE_READ_HITMEM_CAP_WRITE_TAG_SETFP_COMPLETEDMIPS16_COMPLETEDDCACHE_ACCESSESLOAD_MISS_CONSUMER_REPLAYSCLKICACIMISSWBUFFLPMON_EXCEPTDST_STREAM_0_CACHE_LINE_FETCHESVTQ_SUSPENDS_DUE_TO_CTX_CHANGELSU_INDEXED_ALIAS_STALLLS_LM_INSTR_PIECESFAST_BTIC_HITCYCLES_NO_INSTR_DISPATCHEDSS_SM_INSTR_PIECESBUS_RETRYBUS_RETRY_DUE_TO_PREVIOUS_ADJACENTMARKED_GROUP_COMPLETE_TIMEOUTINSTR_MMU_VSP_RELOADSL2_CACHE_ALLOCATIONSFPU_DIVIDE_CYCLESinstructionsmemory-controller-hi-pri-bypassprobe-missbuffer-releaseINTEL_P6INTEL_SANDYBRIDGEINTEL_SANDYBRIDGE_XEONARMV7_CORTEX_A15event{"type": "pmcdetach"{"type": "proccsw"%s, "pmcid": "0x%08x", "pid": "%d", "start": "0x%016jx", "pathname": "%s"}
%s, "pid": "%d", "start": "0x%016jx", "pathname": "%s"}
v8GenuineIntel-6-[4589]EGenuineIntel-6-2AGenuineIntel-6-86Fraction of cycles where both hardware threads were activeumask=0x1,period=2000003,event=0x48This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)This event counts the number of L2 cache lines filling the L2. Counting does not cover rejectsCycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQUops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accessesThis event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. 
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cyclestx_mem.abort_hle_elision_buffer_unsupported_alignmentCounts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional regionumask=0x10,period=2000003,event=0xc8hle_retired.aborted_misc5Loads with latency value being above 8  Spec update: BDM100, BDM35 (Must be precise)otherThis event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another threadcpu_clk_thread_unhalted.ref_xclkNot taken macro-conditional branchesThis event counts both taken and not taken speculative and retired indirect branches excluding calls and return branchesTaken speculative and retired mispredicted indirect callsbr_misp_exec.all_conditionalbr_misp_exec.all_indirect_jump_non_call_retumask=0x20,any=1,period=2000003,event=0xa1cycle_activity.stalls_l2_pendingCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand load requestmachine_clears.maskmovThis is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired (Precise event)umask=0x0,period=400009,event=0xc5Count cases of saving new LBRLLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox umask=0x3,event=0x35,filter_opc=0x1c8,filter_tid=0x3eread requests to home agent. Unit: uncore_ha uncore memorywrite requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc power_channel_ppd %unc_p_clockticksunc_p_power_state_occupancy.cores_c6Counts the number of cycles when current is the upper limit on frequency. Unit: uncore_pcu umask=0x20,period=2000003,event=0x8Store misses in all DTLB levels that cause page walks  Spec update: BDM69tlb_flush.dtlb_threadbdw metrics4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))(( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branchesL3_Cache_Fill_BWCache_MissesCounts demand data reads have any response typeoffcore_response.demand_rfo.l3_hit.snoop_not_neededoffcore_response.corewb.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010010offcore_response.pf_l2_data_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020040offcore_response.pf_l2_code_rd.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0200umask=0x10,edge=1,period=2000003,cmask=1,event=0x79This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
 a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
 b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); 
 c. Instruction Decode Queue (IDQ) delivers four uopsCounts randomly selected loads with latency value being above eight  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000001offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwdoffcore_response.demand_rfo.l3_hit.snoop_non_dramoffcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000020offcore_response.other.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020120This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling (Precise event)umask=0x1,edge=1,period=100003,cmask=1,event=0xc3unc_cbo_cache_lookup.write_mUnit: uncore_cbox L3 Lookup read request that access cache and found line in E or S-stateL3 Lookup write request that access cache and found line in E or S-stateRetired load uops with L1 cache hits as data sources  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC007F7Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cacheCounts all prefetch (that bring data to LLC only) RFOs miss in the L3This event counts both direct and indirect near call instructions retired (Precise event)l2_st.self.m_statel2_ld_ifetch.self.i_stateSIMD packed micro-ops executedSIMD packed logical micro-ops executedDecode stall due to IQ fullLoad splitsbus_trans_brd.selfbus_trans_io.all_agentsumask=0x40,period=200000,event=0x70umask=0x81,period=2000000,event=0x12Multiply operations retiredumask=0x0,period=2000000,event=0xabr_inst_type_retired.ind_callbr_inst_decodedBogus branchesLoad uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM).  More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data.  Loads that obtain a HITM response incur greater latency than most is typical for a load.  In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value.  This event is useful for locating sharing, false sharing, and contended locks  Supports address when precise (Must be precise)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.any_read.l2_miss.hit_other_core_no_fwdCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.hitm_other_coreoffcore_response.any_data_rd.l2_miss.hit_other_core_no_fwdCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystemCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000800umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000080Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x2,period=200003,event=0x13umask=0x2,period=200003,event=0xcbumask=0x10,period=200003,event=0x3Retired branch instructions (Precise event capable) (Must be precise)umask=0xeb,period=200003,event=0xc4Retired near indirect call instructions (Precise event capable) (Must be precise)Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise)umask=0x4,period=200003,event=0x81Counts load uops retired that caused a DTLB miss  Supports address when precise (Must be precise)offcore_response.corewb.outstandingCounts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010020Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededCounts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cacheoffcore_response.any_rfo.outstandingCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleumask=0x8,period=20003,event=0xc3Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache  Spec update: HSD78Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 missNumber of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event)offcore_response.all_requests.l3_miss.any_responseInstructions retired from execution  Spec update: HSD140, HSD143Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threadsThis events counts the cycles where at least two uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise)unc_cbo_xsnp_response.miss_externalCompleted page walks due to demand load misses that caused 2M/4M page walks in any TLB levelsMiss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G)This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walksCounts the number of Extended Page Table walks from the ITLB that hit in the L2umask=0x20,period=100003,event=0xbdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400001Counts the number of near return instructions retired (Precise event)l2_store_lock_rqsts.alll2_l1d_wb_rqsts.missNot rejected writebacks from L1D to L2 cache lines in any stateCore-originated cacheable demand requests missed LLCRetired load uops which data sources missed LLC but serviced from local dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000107F7Number of transitions from SSE to AVX-256 when penalty applicableDecode Stream Buffer (DSB)-to-MITE switchesint_misc.recovery_stalls_countCycles the RS is empty for the threadNumber of instructions at retirementCounts the number of allocated write entries, include full, partial, and LLC evictionsCounts the number of LLC evictions allocatedCycle PMH is busy with a walkCounts L2 hints sent to LLC to keep a line from being evicted out of the core cachesoffcore_response.pf_l2_data_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20004Counts all demand code reads that miss the LLC  and the data returned from local dramCounts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00001Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dramoffcore_response.pf_l2_data_rd.llc_miss.remote_dramPCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current. Unit: uncore_cbox unc_p_freq_ge_2000mhz_transitionsNumber of GSSE-256 Computational FP single precision uops issued this cycleumask=0x2,period=2000003,event=0x4eumask=0x90,period=200003,event=0x89umask=0xd0,period=200003,event=0x89umask=0x80,period=2000003,event=0x59Counts the cycles of stall due to lack of load buffersumask=0x10,period=400009,event=0xc5umask=0x1,edge=1,period=100003,cmask=1,event=0x14Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0resource_stalls.ooo_rsrcevent=0x1umask=0x1,period=200003,event=0x4offcore_response.any_code_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeCounts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier detailsumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000022Counts any Read request  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_request.l2_hit_this_tile_eCounts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180044offcore_response.bus_locks.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000044Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Faroffcore_response.any_request.ddr_nearCounts Software Prefetches that accounts for data responses from DRAM Localoffcore_response.uc_code_reads.mcdram_faroffcore_response.uc_code_reads.mcdram_nearCounts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Localoffcore_response.demand_rfo.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000001Counts the number of near RET branch instructions retired (Precise event)Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrtL1 data cache stores in M statel1d_cache_st.s_stateL2 data demand loads in E statel2_rqsts.ifetch_missL2 instruction fetch missesumask=0x8,period=200000,event=0x24l2_rqsts.rfosl2_write.rfo.hitLongest latency cache referencemem_inst_retired.loadsOffcore requests satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x422Offcore writebacks to the LLC or local DRAMOffcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unitOffcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling coreoffcore_response.demand_data.llc_hit_no_other_coreOffcore demand data requests satisfied by the LLC and HIT in a sibling coreOffcore demand data requests satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x701offcore_response.demand_ifetch.llc_hit_other_core_hitoffcore_response.pf_data.any_cache_dramOffcore prefetch data reads satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1840umask=0x1,period=100000,event=0xb7,offcore_rsp=0x720Offcore prefetch RFO requests satisfied by the LLCOffcore prefetch RFO requests satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x470umask=0x1,period=100000,event=0xb7,offcore_rsp=0x870SSE and SSE2 FP Uopsumask=0x1,period=200000,event=0x12simd_int_128.unpackSIMD integer 64 bit packed multiply operationsoffcore_response.any_request.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF808offcore_response.pf_ifetch.any_dramlarge_itlb.hitAll loads dispatchedAll Store buffer stall cyclesarith.cycles_div_busyDivide Operations executedumask=0x1,period=200000,event=0xc4br_misp_exec.directinst_queue_writesssex_uops_retired.packed_singleuops_executed.port3_coreMacro-fused Uops retired (Precise Event)offcore_response.demand_code_rd.l4_hit_local_l4.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0400004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000088000Requests from the L1/L2/L3 hardware prefetchers or Load software prefetchesperiod=200003,umask=0x2,event=0xf2offcore_response.demand_rfo.l3_hit_e.spl_hitoffcore_response.demand_rfo.l3_hit_e.snoop_not_neededoffcore_response.other.l3_hit_s.snoop_hitmRetired load instructions that miss the STLB  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200108000period=200003,umask=0xff,event=0x24Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001C0002Counts any other requestshave any response typeperiod=100003,umask=0x2,event=0xb0offcore_response.other.l4_hit_local_l4.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001C8000Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=100007,umask=0x1,event=0xc6,frontend=0x400106cmask=1,inv=1,period=2000003,umask=0x1,event=0x9cRetired Instructions who experienced Instruction L1 Cache true miss (Precise event)rtm_retired.aborted_memoffcore_response.demand_rfo.l3_miss_local_dram.spl_hitoffcore_response.demand_data_rd.l3_miss_local_dram.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC400002period=101,umask=0x1,event=0xcd,ldlat=0x200period=100003,umask=0x1,event=0xb7,offcore_rsp=0x20001C0001period=100003,umask=0x1,event=0xcd,ldlat=0x4period=50021,umask=0x1,event=0xcd,ldlat=0x8Far branch instructions retired  Spec update: SKL091 (Precise event)cmask=3,period=2000003,umask=0x1,event=0xb1cmask=4,period=2000003,umask=0x1,event=0xa8Loads blocked due to overlapping with a preceding store that cannot be forwardedperiod=25003,umask=0x2,event=0x3cperiod=2000003,umask=0x1,event=0xa2exe_activity.exe_bound_0_portscmask=1,period=100003,umask=0x10,event=0x85period=100003,umask=0x8,event=0x85Page walk completed due to a demand data load to a 4K pageCycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylakerehabq.any_ldLoads missed L1All LoadsCounts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cacheCounts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedMachine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path.  All instructions "older" than this one will be allowed to finish.  This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete.  Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine.  This means all older instructions are retired, and all pending stores (from older instructions) are completed.  Then the new path of instructions from the front end are allowed to start into the machine.  There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault).  All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST).  However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANYThis event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walksThis event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksCounts all prefetch data reads that hit in the LLCoffcore_response.pf_l2_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400080Actually retired uops. (Precise Event - PEBS) (Precise event)REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f33REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIOoffcore_response.other.all_local_dram_and_remote_cache_hitREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAMoffcore_response.data_in.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3001umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3004umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3002umask=0x4,period=100000,event=0xb4umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2722umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2750umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5810offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwdOFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0004Counts all prefetch (that bring data to LLC only) data reads that have any response typeoffcore_response.pf_l3_data_rd.l3_hit.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0080offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwdCounts prefetch RFOs that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l2_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800020offcore_response.pf_l3_rfo.l3_miss.remote_hitmskx metricsL2Evicts;ServerAverage_FrequencyMMIO writes. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha 7.11E-06Bytesfc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83,ch_mask=0x1fCounts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not neededMulti-socket cacheline Directory state lookups; Snoop Needed. Unit: uncore_cha unc_cha_imc_writes_count.fullLines Victimized; Lines in F State. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to it's home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in >= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to it's home socket to be written back to memoryfc_mask=0x04,umask=0x04,event=0xd5unc_iio_data_req_by_cpu.mem_read.part1Read request for 4 bytes made by the CPU to IIO Part1. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc0fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc0unc_iio_data_req_by_cpu.peer_read.part3fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x83unc_iio_txn_req_by_cpu.mem_read.part0unc_iio_txn_req_by_cpu.peer_write.part3Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overriddenAD Ingress (from CMS) Occupancy. Unit: uncore_m2m BL Ingress (from CMS) Occupancy. Unit: uncore_m2m umask=0x03,event=0x16FLITs received which bypassed the Slot0 Recieve Buffer. Unit: uncore_upi ll umask=0x27,event=0x3mem_load_l3_miss_retired.remote_pmmperiod=100003,umask=0x80,event=0xd1offcore_response.all_data_rd.l3_hit_e.any_snoopoffcore_response.all_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080491offcore_response.all_data_rd.l3_hit_e.snoop_noneoffcore_response.all_data_rd.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800807F7offcore_response.all_reads.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001007F7This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwdoffcore_response.demand_code_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_s.no_snoop_neededoffcore_response.demand_data_rd.l3_hit_e.hitm_other_coreoffcore_response.demand_data_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200002offcore_response.other.l3_hit.hit_other_core_fwdoffcore_response.other.l3_hit.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISSoffcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040010offcore_response.pf_l2_data_rd.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwdoffcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200100( 1000000000 * ( imc@event\=0xe0\,umask\=0x1@ / imc@event\=0xe3@ ) / imc_0@event\=0x0@ )OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_data_rd.l3_miss_local_dram.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000120ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F900007F7ocr.all_rfo.l3_miss_local_dram.any_snoopocr.all_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000122ocr.demand_code_rd.l3_miss.hit_other_core_fwdocr.demand_code_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000004Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.demand_rfo.l3_miss.snoop_missCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONECounts any other requests OCR.OTHER.L3_MISS.REMOTE_HITMocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_coreCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l2_rfo.l3_miss.snoop_noneocr.pf_l2_rfo.l3_miss_local_dram.snoop_missCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoopCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000100ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_coreoffcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.other.l3_miss_remote_hop1_dram.any_snoopoffcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_coreoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_neededocr.all_data_rd.l3_hit.no_snoop_neededocr.all_data_rd.l3_hit_f.any_snoopocr.all_data_rd.l3_hit_f.hitm_other_coreocr.all_data_rd.l3_hit_m.hit_other_core_fwdocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwdocr.all_pf_rfo.l3_hit_m.any_snoopocr.all_pf_rfo.l3_hit_m.no_snoop_neededOCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_reads.l3_hit_e.hitm_other_coreOCR.ALL_READS.L3_HIT_F.SNOOP_MISSOCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_m.snoop_missocr.all_reads.l3_hit_s.hit_other_core_fwdocr.all_rfo.l3_hit_e.any_snoopOCR.ALL_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_E.ANY_SNOOPocr.all_rfo.l3_hit_e.snoop_noneOCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_f.snoop_missOCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit.hit_other_core_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDEDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDCounts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORECounts any other requests  OCR.OTHER.L3_HIT_F.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit.snoop_noneocr.pf_l1d_and_sw.l3_hit_f.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDEDCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOPCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOPCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDWritesTag Check; Hitperiod=100003,umask=0x20,event=0xc7DSB-to-MITE switch true penalty cyclesperiod=100007,umask=0x1,event=0xc6,frontend=0x502006cpu_clk_unhalted.distributedCycles where data return is pending for a Demand Data Read request who miss L3 cacheperiod=100003,umask=0x2,event=0x54period=100003,umask=0x1,event=0xc8Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestCounts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionsocr.demand_data_rd.dramCounts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000400ocr.hwpf_l2_rfo.l3_hit.snoop_not_neededCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9Counts cycles where the Store Buffer was full and no loads caused an execution stallbr_inst_retired.cond_takenperiod=50021,umask=0x1,event=0xc5( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending ) / ( 2 * core_clks )( unc_cha_tor_inserts.io_hit_itom + unc_cha_tor_inserts.io_miss_itom + unc_cha_tor_inserts.io_hit_itomcachenear + unc_cha_tor_inserts.io_miss_itomcachenear ) * 64 / 1000000000 / duration_timeumask=0x30,event=0x4umask=0x10,event=0x2event=0x83unc_cha_tor_inserts.iaTOR Occupancy : RFOs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_crd_prefunc_cha_tor_inserts.ia_drd_prefTOR Inserts : CRDs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_remotefc_mask=0x07,ch_mask=0x01,umask=0x80,event=0x83fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0x83Number requests PCIe makes of the main die : All. Unit: uncore_iio unc_iio_txn_req_by_cpu.mem_read.part5fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0x84unc_iio_txn_req_of_cpu.cmpd.part7fc_mask=0x07,ch_mask=0x80,umask=0x80,event=0x84unc_iio_comp_buf_inserts.cmpd.part7PCIe Completion Buffer Occupancy of completions with data : Part 0. Unit: uncore_iio unc_m2p_clockticksumask=0xC867FE01,event=0x35Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cacheThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSEtopdown_be_bound.alloc_restrictionsCounts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uopsperiod=1000003,umask=0x2,event=0x71Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page faultThe number of 64 byte instruction cache line was fulfilled from the L2 cacheAll L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon eventumask=0x20,event=0x63Retired Taken Branch Instructions Mispredictedremote_outbound_data_controller_3dram_channel_data_controller_7Single-precision multiply FLOPSevent=0x40ls_l1_d_tlb_miss.allls_tablewalker.isidede_dis_dispatch_token_stalls0.alsq3_token_stallL2 Cache Accesses from L1 Data Cache Misses (including prefetch)L1 ITLB MissesL1 Branch Prediction Overrides Existing Prediction (speculative)umask=0xff,event=0x94x87 bottom-executing uOps retired. The number of serializing Ops retiredevent=0x2bHardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote)Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination registerumask=0x08,event=0xaeInstruction Cache Miss. Counts various IC tag related hit and miss eventsxi_ccx_sdp_req1Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedumask=0x50,event=0x44macro_ops_retiredFP_CYCLES_WITH_NO_FPU_OPS_RETIREDPRED_BRANCH_PRED_TAKENINSTRUCTIONS_ISSUED_CYCLEEVENT_19HEVENT_4AHEVENT_62HEVENT_A2HEVENT_B1HEVENT_BAHEVENT_BBHEVENT_D7HEVENT_DCHEVENT_E2HEXC_IRQL1D_TLB_REFILL_STEXC_SVCL2_MISSWBB_LT_QUARTERIFU_IDU_CLOGED_DOWNSTREAM_CYCLESCLDQ_FULL_DR_STALLSJTLB_DATA_MISSESVA_TRANSALTION_CORNER_CASESCP1_CP2_COND_BRANCH_INSNSMIPS16_INSNSDSPRAM_EVENTSNISSUEBRECDDIDSTOUCH_ALIASL1_DATA_SNOOP_HIT_CASTOUT_QUEUECACHE_INHIBITED_STORESSECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYL3_LOAD_HITSPREFETCH_ENGINE_COLLISION_VS_INSTR_FETCHPREFETCH_ENGINE_FULLMARKED_INSTR_FINISH_ANY_UNITREJECT_COMPLETION_STALL_ERAT_MISSLOAD_GUARDED_MISSDATA_MMU_VSP_RELOADSL2_CACHE_UPDATESDECORATED_STORESk8-dc-missespage-conflictMIPS24KINTEL_PIIls_int_takenBR_MISP_RETIRED.ALL_BRANCHESfc_mask%s, "pmcid": "0x%08x", "pid": "%d", "pathname": "%s"}
GenuineIntel-6-3AGenuineIntel-6-3EIFetch_Line_Utilizationinst_retired.any / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cyclesumask=0x30,period=200003,event=0x24umask=0xe4,period=200003,event=0x24Cycles when L1D is lockedumask=0x4,period=50021,event=0xd1umask=0x2,period=200003,event=0xf0l2_trans.l1d_wbNumber of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementumask=0x18,cmask=4,period=2000003,event=0x79This event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQumask=0x3c,period=2000003,event=0x79Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalledmemoryumask=0x20,period=2000003,event=0x54Number of times we could not allocate Lock BufferThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. 
Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this caseTaken speculative and retired mispredicted indirect branches with return mnemonicumask=0x4,period=2000003,event=0xa1Cycles per thread when uops are executed in port 7resource_stalls.anyumask=0x1,cmask=3,period=2000003,event=0xb1Cycles where at least 3 uops were executed per-threadCycles at least 2 micro-op is executed from any thread on physical coreThis is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight  Supports address when precise (Precise event)This event counts self-modifying code (SMC) detected, which causes a machine clearMaskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a faultConditional branch instructions retired. (Precise Event - PEBS) (Precise event)br_inst_retired.near_call_r3umask=0x4,period=400009,event=0xc4Far branch instructions retired  Spec update: BDW9864BytesPCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox (unc_p_freq_max_power_cycles / unc_p_clockticks) * 100.umask=0xe,period=100003,event=0x49umask=0x1,period=100007,event=0xaepage_walker_loads.dtlb_l11 - ( (idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) )uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))idq.dsb_uops / (( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops ) )uops_executed.thread / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else uops_executed.cycles_ge_1_uop_exec)BrMispredicts1000 * ( l2_rqsts.references - l2_rqsts.miss ) / inst_retired.any1000 * mem_load_uops_retired.l3_miss / inst_retired.anyumask=0xc1,period=200003,event=0x24offcore_response.demand_data_rd.l3_hit.snoop_noneoffcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0008offcore_response.pf_l2_rfo.supplier_none.snoop_missoffcore_response.pf_l2_code_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020080offcore_response.pf_l3_rfo.l3_hit.snoop_not_neededCounts all prefetch data readsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0091Randomly selected loads with latency value being above 4  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000001offcore_response.demand_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000008offcore_response.corewb.l3_miss.snoop_hit_no_fwdoffcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000010offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000100offcore_response.other.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwdoffcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000091offcore_response.all_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000122umask=0x8f,event=0x34Number of Core coherent Data Read entries allocated in DirectData modecbox_0@event\=0x0@Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)umask=0x50,period=200000,event=0x24L2 cacheable instruction fetch requestsumask=0x48,period=200000,event=0x28umask=0x48,period=200000,event=0x2dumask=0x4f,period=200000,event=0x2eL1 Cacheable Data WritesSIMD packed shift micro-ops executedumask=0x84,period=200000,event=0x7umask=0xe0,period=200000,event=0x63umask=0x22,period=200000,event=0x77umask=0x28,period=200000,event=0x77bus_io_wait.selfcycles_int_masked.cycles_int_maskedMispredicted indirect calls, including both register and memory indirectumask=0x1,period=2000000,event=0xe0umask=0x1,period=200000,event=0x3Memory accesses that missed the DTLBDTLB misses due to load operationsdata_tlb_misses.l0_dtlb_miss_ldumask=0xa,period=200000,event=0x8umask=0x2,period=200000,event=0xcCounts locked memory uops retired.  This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.)  A locked access is one with a lock prefix, or an exchange to memory.  See the SDM for a complete description of which memory load accesses are locks  Supports address when precise (Must be precise)umask=0x81,period=200003,event=0xd0Counts the number of load uops retired  Supports address when precise (Must be precise)mem_load_uops_retired.hitmMemory uop retired where cross core or cross module HITM occurred (Precise event capable)  Supports address when precise (Must be precise)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cacheoffcore_response.any_data_rd.l2_miss.anyoffcore_response.any_pf_data_rd.l2_miss.anyCounts data cache lines requests by software prefetch instructions that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000800offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwdCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwdCounts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not countUnfilled issue slots per cycle to recoverCounts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction QueueCounts uops retired that are from the complex flows issued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise)uops_retired.idivCounts near CALL branch instructions retired (Must be precise)baclears.allCounts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000002000Counts requests to the uncore subsystem have any transaction responses from the uncore subsystemumask=0x2,period=20003,event=0xc3umask=0x0,period=20003,event=0xc3umask=0x4,period=200003,event=0x8This event counts each cache miss condition for references to the last level cacheumask=0x2,period=2000003,event=0x48Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD78, HSD62, HSD61Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61Retired load uops that miss the STLB. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cyclesNumber of times an HLE execution successfully committedoffcore_response.all_rfo.l3_miss.any_responseoffcore_response.all_data_rd.l3_miss.local_dramumask=0x2,period=100003,event=0xc4umask=0x40,period=100003,event=0xc4unc_cbo_cache_lookup.write_iDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)Store misses in all DTLB levels that cause completed page walks. (1G)ITLB misses that hit STLB. No page walkNumber of DTLB page walker loads that hit in the L2Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FBThis event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event)Counts any demand and L1 HW prefetch data load requests to L2Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queueOffcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cyclesmem_load_uops_retired.llc_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10008Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.split_lock_uc_lock.any_responseNumber of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycleCycles DSB to MITE switches caused delayCounts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dramUnit: uncore_cbox A snoop invalidates a modified line in some processor coreNumber of requests allocated in Coherency Trackerumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c03f7offcore_response.all_code_rd.llc_miss.remote_hit_forwardCounts all demand & prefetch data reads that hits the LLCCounts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cacheumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820010umask=0x1,event=0x35,filter_opc=0x1e6freq_band1_cycles %event=0xb,edge=1,filter_band0=12l1d.evictionRFOs that hit cache lines in E stateidq_uops_not_delivered.cycles_ge_1_uop_deliv.coreoffcore_response.all_demand_mlc_pref_reads.llc_miss.any_responseuops_dispatched.coreEach cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED eventresource_stalls2.all_fl_emptyCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of load micro-ops retired that miss in L1 D cacheCounts the number of load micro-ops retired that miss in the L2  Supports address when precise (Precise event)Counts any Prefetch requests that accounts for any responseCounts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800081000Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.partial_reads.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080040Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_rfo.l2_hit_this_tile_mCounts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in E stateCounts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.demand_data_rd.l2_hit_this_tile_foffcore_response.demand_rfo.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180002Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400070Counts any Prefetch requests that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x01010032f7Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM LocalCounts Software Prefetches that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800400offcore_response.partial_reads.mcdram_nearCounts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200040offcore_response.pf_l2_code_rd.ddr_farCounts demand code reads and prefetch code reads that accounts for data responses from MCDRAM LocalCounts Demand cacheable data writes that accounts for data responses from DRAM Localoffcore_response.demand_data_rd.ddr_farCounts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far)no_alloc_cycles.rat_stallCounts the total number of core cycles when no micro-ops are allocated for any reasonCounts the number of unhalted reference clock cyclesCounts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front endrecycleq.any_stmcdram bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk l1d.m_replL2 data demand loads in M statel2_lines_out.prefetch_cleanumask=0xff,period=200000,event=0x24mem_load_retired.llc_missRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)umask=0x10,period=10000,event=0xb,ldlat=0x10mem_inst_retired.latency_above_threshold_4096offcore_response.any_data.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8011Offcore data reads satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3811umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FFFoffcore_response.any_rfo.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x822umask=0x1,period=100000,event=0xb7,offcore_rsp=0x108umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8003Offcore demand data reads satisfied by the LLC and HIT in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF02offcore_response.demand_rfo.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8080Offcore other requests satisfied by the IO, CSR, MMIO unitoffcore_response.pf_data.any_locationoffcore_response.pf_data.llc_hit_no_other_coreoffcore_response.pf_data_rd.any_locationoffcore_response.pf_ifetch.llc_hit_other_core_hitmOffcore prefetch RFO requests satisfied by the LLC and not found in a sibling coreSSE* FP double precision Uops128 bit SIMD integer shift operationssimd_int_128.shuffle_moveumask=0x10,period=200000,event=0xfdumask=0x2,period=200000,event=0xfdoffcore_response.any_data.any_llc_missOffcore code reads satisfied by the local DRAMoffcore_response.any_ifetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2008offcore_response.data_ifetch.any_dramoffcore_response.demand_data.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4004Offcore demand RFO requests satisfied by a remote DRAMoffcore_response.other.any_dramOffcore prefetch RFO requests satisfied by any DRAMOffcore prefetch requests that missed the LLCOffcore prefetch requests satisfied by the local DRAMI/O transactionsumask=0x4,period=2000000,event=0x13rat_stalls.rob_read_portbr_inst_exec.indirect_near_callAll non call branches executedMispredicted branches executedInstructions that must be decoded by decoder 0umask=0x1,period=20000,event=0xc3uops_executed.port015_stall_cyclesumask=0x2,period=2000000,event=0xeinst_retired.total_cycles_psumask=0x20,period=200000,event=0xc8umask=0x80,period=200000,event=0xcbCounts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheCounts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3  Spec update: SKL057offcore_response.demand_data_rd.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001C0001offcore_response.demand_data_rd.l4_hit_local_l4.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040004Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncoreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0048000period=2000003,umask=0x1,event=0x48L1D miss outstandings duration in cyclesperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000018000cmask=6,period=2000003,umask=0x10,event=0x60offcore_response.demand_rfo.supplier_none.snoop_non_dramperiod=2000003,umask=0x1,event=0x5dperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C400004hle_retired.aborted_memperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000100004rtm_retired.aborted_eventsCounts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise (Must be precise)Number of PREFETCHNTA instructions executedCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization GuideCounts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current threadbr_inst_retired.cond_ntakencmask=1,inv=1,period=2000003,umask=0x2,event=0xc2period=400009,umask=0x4,event=0xc4int_misc.clear_resteer_cyclesperiod=100007,umask=0x1,event=0xbdrehabq.ld_block_std_notreadyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018008Counts demand and DCU prefetch data read that miss L2TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)All retired load uops. (Precise Event - PEBS) (Precise event)offcore_response.all_pf_rfo.llc_hit.hitm_other_coreCounts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts all prefetch (that bring data to L2) data reads that hit in the LLCCounts all prefetch (that bring data to L2) RFOs that hit in the LLCCounts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_code_rd.llc_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0100REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.data_in.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff03umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff80REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f40REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x30ffoffcore_response.any_rfo.other_local_dramREQUEST = PF_RFO and RESPONSE = REMOTE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5822umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5877umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5803period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0491offcore_response.all_pf_data_rd.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0120offcore_response.all_rfo.l3_hit.no_snoop_neededoffcore_response.demand_code_rd.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010020Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per elementoffcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00122Counts demand data reads that miss the L3 and the data is returned from local or remote dramoffcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dramoffcore_response.pf_l3_data_rd.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00100cpu_clk_unhalted.thread_p:k / cpu_clk_unhalted.threadunc_iio_data_req_of_cpu.mem_write.part2unc_cha_core_snp.evict_gtoneumask=0x02,event=0x54umask=0x01,event=0x5bIngress (from CMS) Request Queue Rejects; PhyAddr Matchunc_iio_comp_buf_inserts.cmpd.part2fc_mask=0x04,umask=0x01,event=0xd5Write request of 4 bytes made to IIO Part1 by the CPU. Unit: uncore_iio fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc0Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busRead request for up to a 64 byte transaction is made by the CPU to IIO Part0. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit. Unit: uncore_iio fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x84unc_iio_txn_req_of_cpu.mem_write.part3umask=0x10,event=0x2eumask=0x80,event=0x38Prefetches generated by the flow control queue of the M3UPI unit. Unit: uncore_m3upi This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_neededoffcore_response.all_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080490offcore_response.all_pf_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020490offcore_response.all_pf_rfo.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040120This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C07F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000207F7offcore_response.all_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwdoffcore_response.demand_rfo.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020002offcore_response.other.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80048000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwdoffcore_response.pf_l2_rfo.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040080offcore_response.pf_l3_data_rd.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080100PMM_Write_BWocr.all_pf_data_rd.l3_miss.any_snoopocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdOCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITMOCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_rfo.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_code_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000004Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOPCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC08000Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090008000ocr.pf_l1d_and_sw.l3_miss.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.pf_l2_rfo.l3_miss.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000080Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000100ocr.pf_l3_rfo.l3_miss_local_dram.any_snoopoffcore_response.all_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_miss.snoop_missoffcore_response.all_reads.l3_miss_local_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoopocr.all_data_rd.l3_hit.snoop_noneOCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_s.hitm_other_coreOCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.pmm_hit_local_pmm.any_snoopocr.all_reads.l3_hit_f.no_snoop_neededocr.all_rfo.supplier_none.no_snoop_neededocr.demand_code_rd.l3_hit.snoop_missocr.demand_code_rd.l3_hit_e.any_snoopocr.demand_code_rd.l3_hit_f.hitm_other_coreocr.demand_code_rd.l3_hit_m.snoop_noneCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.supplier_none.snoop_noneocr.demand_rfo.l3_hit_f.snoop_noneocr.demand_rfo.supplier_none.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_s.snoop_noneocr.pf_l1d_and_sw.l3_hit.any_snoopocr.pf_l1d_and_sw.l3_hit.no_snoop_neededocr.pf_l1d_and_sw.l3_hit_f.hitm_other_coreocr.pf_l2_data_rd.l3_hit_e.snoop_missocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwdocr.pf_l3_data_rd.l3_hit.hitm_other_coreocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwdumask=0x2,event=0xeaTag Check; Dirtyunc_cha_tor_occupancy.ia_miss_drdDirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m unc_m2m_tag_hit.nm_ufill_hit_cleanCycles the superQ cannot take any more entriesperiod=100021,umask=0x10,event=0xd1period=1000003,umask=0x4,event=0x60Cycles MITE is delivering optimal number of Uopsperiod=100003,umask=0x2,event=0xabperiod=100003,umask=0x4,event=0xc8ocr.hwpf_l2_data_rd.l3_missCounts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cacheperiod=100003,umask=0x80,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000800ocr.hwpf_l2_rfo.l3_hit.snoop_hitmassists.anyocr.hwpf_l1d_and_swpf.l3_hit.snoop_not_neededCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of responseCounts taken branch instructions retired (Precise event)A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event)misc_retired.pause_instlsd.cycles_okFor every cycle where the core is waiting on at least 1 outstanding demand data read request, increments by 1icx metricsunc_m_dram_refresh.opportunisticumask=0x04,event=0x45Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha Remote read requests sent to the CHA's home agent. Unit: uncore_cha TOR Inserts : All requests from IO Devices that hit the LLC. Unit: uncore_cha TOR Occupancy : All requests from iA Cores. Unit: uncore_cha unc_iio_data_req_by_cpu.mem_read.part4Responses to snoops of any type that hit M line in the IIO cache. Unit: uncore_irp umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000002TOR Inserts; CRd Pref misses from local IA. Unit: uncore_cha period=200003,umask=0x20,event=0x34period=200003,umask=0x1,event=0xe9ocr.demand_data_and_l1pf_rd.l3_miss_localbus_lock.block_cyclesThis event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HITCounts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path (Precise event)ept.epdpe_hitept.epdpe_missperiod=200003,umask=0x4,event=0x81event=0x8ebp_l1_tlb_miss_l2_hitic_cache_inval.fill_invalidatedl2_request_g1.change_to_xl2_request_g2.group1Miscellaneous events covered in more detail by l2_request_g1 (PMCx060)l2_request_g2.ls_rd_sizedumask=0x40,event=0x61umask=0x20,event=0x61All L2 Cache Requests (Breakdown 2 - Rare). Bus locksCore to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types)l2_cache_req_stat.ic_fill_hit_sl2_cache_req_stat.ic_dc_hit_in_l2ex_ret_mmx_fp_instr.x87_instrex_div_countDRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0umask=0x38,event=0xc7umask=0x04,event=0The number of serializing Ops retired. SSE bottom-executing uOps retiredls_l1_d_tlb_miss.tlb_reload_2m_l2_hitumask=0x01,event=0x46Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailableL2 Cache Hits from L1 Instruction Cache Missesl3_missesl3_read_miss_latencyl3_cache6.1e-5MiBL2 Branch Prediction Overrides Existing Prediction (speculative)Retired lock instructions. Non-speculative lock succeededDemand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different dieumask=0x40,event=0x59ls_sw_pf_dc_fill.ls_mabresp_lcl_l2umask=0x02,event=0xaaCore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2The number of macro-ops retiredex_ret_msprd_brnch_instr_dir_msmtchSSE/AVX control word mispredict traps. The number of serializing Ops retiredumask=0x08,event=0x44ls_misal_loads.ma64Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stallCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination registerCycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1IC_FETCHNB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWEVENT_1AHEVENT_54HEVENT_58HEVENT_5FHEVENT_8AHEVENT_8CHEVENT_C7HEVENT_DAHEVENT_EFHEVENT_F5HISSUE_DNOT_DISPATCH_ANY_INSTRDATA_MICRO_TLB_MISS_STALLPLE_FIFO_FLUSHL1I_TLB_REFILLMEMORY_ERRORUNALIGNED_LDST_SPECST_SPECEXC_TRAP_PABORTMEM_WORD_READMEM_DWORD_READRETURN_NOT_31BARRIER_COMPLETEDUNCACHED_STORECP2_REG_TO_REG_COMPLETEDOOO_AGEN_ISSUE_CYCLESJALR_JALR_HB_INSNSMISPREDICTED_JR_31_INSNSJ_JAL_INSNSWBB_LESS_25_FULLUUSTORECPREFTHRESHOLD_INSTR_QUEUE_ENTRIES_CYCLESL1_INSTR_CACHE_ACCESSESWRITE_THROUGH_STORESLSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1L1_DATA_TOTAL_MISSL2_LOAD_HITSSNOOP_VALIDL2_VALID_REQUESTSRQ_EMPTYDATA_MMU_MISSSNOOP_HITSSTASH_BUSY_3L2_INCOHERENT_LINE_INVALIDATIONSCOHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHESscrubbermissestag-snoopx87-reclass-microfaultsINVERTINTEL_ICELAKE_XEONARMV8_CORTEX_A53state errorunit: %s
{"type": "pmcallocate"GenuineIntel-6-5FGenuineIntel-6-2DGenuineIntel-6-7DIPCInstructions Per Cycle (per physical core)C7_Core_ResidencyC2 residency percent per packageL2 cache misses when fetching instructionsl2_rqsts.demand_data_rd_hitCycles with L1D load Misses outstanding from any thread on physical coremem_uops_retired.lock_loadsRetired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts transactions that access the L2 pipe including snoops, pagewalks, and so onfp_arith_inst_retired.128b_packed_doubleUops delivered to Instruction Decode Queue (IDQ) from MITE pathumask=0x1,period=2000003,event=0x9cThis event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4umask=0x1,cmask=2,period=2000003,event=0x9cumask=0x2,period=2000003,event=0x5tx_exec.misc1Unfriendly TSX abort triggered by a nest count that is too deepNumber of times an RTM execution aborted due to incompatible memory typeNumber of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)Unhalted core cycles when thread is in rings 1, 2, or 3event=0xc0int_misc.rat_stall_cyclesumask=0x8,period=2000003,event=0xdNumber of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or notumask=0x1,period=2000003,event=0x3cNumber of SIMD Move Elimination candidate uops that were not eliminatedild_stall.lcpTaken speculative and retired macro-conditional branchesumask=0xc4,period=200003,event=0x88This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructionsuops_executed_port.port_5Cycles per core when uops are exectuted in port 6inv=1,umask=0x1,cmask=1,period=2000003,event=0xb1Cycles there was a Nuke. Account for both thread-specific and All Thread Nukesbr_inst_retired.near_returnllc_misses.pcie_non_snoop_writepower_self_refresh %power_state_occupancy.cores_c3 %unc_p_prochot_external_cyclesfreq_max_limit_thermal_cycles %umask=0x2,period=2000003,event=0x8Code misses that miss the  DTLB and hit the STLB (2M)STLB flush attemptsRetiring_SMTTotal issue-pipeline slots (per-Physical Core)Memory_BWumask=0x1,period=2000003,cmask=1,event=0x48umask=0x2,period=2000003,cmask=1,event=0x48offcore_response.demand_data_rd.l3_hit.snoop_hitmoffcore_response.demand_rfo.l3_hit.snoop_noneoffcore_response.demand_code_rd.supplier_none.snoop_not_neededCounts writebacks (modified to exclusive)Counts all prefetch (that bring data to L2) RFOsoffcore_response.other.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020240offcore_response.all_pf_code_rd.l3_hit.snoop_missoffcore_response.all_rfo.supplier_none.snoop_noneThis event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBSumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000001offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000020offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000100offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004008000offcore_response.other.l3_miss.snoop_noneoffcore_response.other.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000240offcore_response.all_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000122umask=0x2,period=2000003,cmask=1,event=0xb1unc_arb_trk_occupancy.drd_direct( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_timeThis event counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event)Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C07F7offcore_response.all_code_rd.llc_miss.any_responseQPI clock ticks. Unit: uncore_qpi l2_m_lines_out.self.anyl2_ld_ifetch.self.e_statel2_rqsts.self.any.i_stateumask=0x4f,period=200000,event=0x30umask=0x51,period=200000,event=0x30L1 Data Cacheable reads and writesmem_load_retired.l2_missx87_comp_ops_exe.any.arsimd_uop_type_exec.mul.sSIMD assists invokedsimd_sat_instr_retiredIcache hitDecode stall due to PFB emptymisalign_mem_ref.split.arbus_lock_clocks.all_agentsumask=0x40,period=200000,event=0x67umask=0x40,period=200000,event=0x68umask=0x20,period=200000,event=0x7abus_hit_drv.this_agentsnoop_stall_drv.all_agentsstore_forwards.anymul.sMispredicted ind branches that are not callsumask=0x1,period=200000,event=0x82Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) that hit the L2 cacheCounts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor moduleCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004000Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000020umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000010Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor moduleDecode restrictions due to predicting wrong instruction lengthCounts anytime a load that retires is blocked for any reason (Must be precise)Uops issued to the back end per cycleumask=0x0,period=200003,event=0xc3Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processorsbaclears.returnDuration of page-walks in cyclesStore uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystemCounts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Integer divide uops retired (Precise Event Capable) (Must be precise)umask=0x10,period=200003,event=0x85All L2 requests  Spec update: HSD78offcore_response.pf_l2_data_rd.l3_hit.any_responseoffcore_response.demand_code_rd.l3_hit.hitm_other_coreCounts cycles MITE is delivered four uops. Set Cmask = 4Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision bufferumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400004Cycles which a uop is dispatched on port 0 in this threadThis events counts the cycles where at least three uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles at least 4 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31unc_cbo_cache_lookup.extsnp_iNumber of ITLB page walker hits in Memory  Spec update: HSD25umask=0x41,period=2000003,event=0xbcoffcore_response.pf_l2_code_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400091l2_rqsts.pf_hitRFOs that hit cache lines in M stateumask=0xf,period=200003,event=0x28Core-originated cacheable demand requests that refer to LLCCycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncoreDemand data read requests sent to uncoreRetired store uops that split across a cacheline boundary. (Precise Event)Counts all demand & prefetch data reads that hit in the LLCCounts all demand code reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010002fp_comp_ops_exe.sse_scalar_doubleCycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) linesmin( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 32 * ( icache.hit + icache.misses ) / 4 ) )offcore_response.all_data_rd.llc_miss.dramCycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of dividesumask=0x4,edge=1,period=100003,cmask=1,event=0x14Cycles per thread when uops are dispatched to port 1Cycles per thread when uops are dispatched to port 4Unit: uncore_cbox A snoop hits a non-modified line in some processor coreumask=0x20,event=0x34Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCCycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesCounts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0080Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from thereCounts demand data reads that miss the LLC  and the data forwarded from remote cacheevent=0xeevent=0xb,edge=1unc_p_freq_ge_3000mhz_transitionsMiss in last-level (L3) cache. Excludes Unknown data-sourceumask=0x2,period=2000003,event=0x51uops_dispatched.thread / (( cpu@uops_dispatched.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_dispatched.core\,cmask\=1@)hw_pre_req.dl1_missResource stalls2 control structures full for physical registersresource_stalls.mem_rsumask=0xa,event=0x36,filter_opc=0x182QPI clock ticks. Used to get percentages of QPI cycles events. Unit: uncore_qpi Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of times that the uncore transistioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu offcore_response.any_read.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400044offcore_response.any_data_rd.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000403091offcore_response.any_request.l2_hit_near_tile_e_fCounts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeCounts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E stateCounts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_read.l2_hit_this_tile_sCounts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_software.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180022Counts any Read request  that accounts for data responses from DRAM Localoffcore_response.any_code_rd.ddr_nearoffcore_response.any_rfo.mcdram_farCounts Bus locks and split lock requests that accounts for data responses from MCDRAM LocalCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM LocalCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM LocalCounts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_software.mcdramCounts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)no_alloc_cycles.rob_fullCounts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is fullbr_misp_retired.callumask=0x01,event=0x3L1 data cache load locks in E stateumask=0x2,period=200000,event=0x4el1d_wb_l2.mesiumask=0x1,period=200000,event=0x26L2 instruction fetch hitsumask=0xc,period=200000,event=0x24umask=0x80,period=200000,event=0xf0l2_transactions.loadL2 demand lock RFOs in E stateumask=0x80,period=100000,event=0x27umask=0x10,period=10000,event=0xcbumask=0x8,period=40000,event=0xcbmem_inst_retired.latency_above_threshold_1024umask=0x10,period=10,event=0xb,ldlat=0x2000Offcore data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_data.local_cache_dramoffcore_response.any_data.remote_cache_hitoffcore_response.any_ifetch.llc_hit_other_core_hitmOffcore code reads satisfied by the LLCAll offcore requestsOffcore RFO requests that HIT in a remote cacheOffcore writebacks to the LLC and not found in a sibling coreOffcore request = all data, response = any locationOffcore data reads, RFO's and prefetches that HITM in a remote cacheOffcore demand data requests satisfied by a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x803Offcore demand data reads satisfied by the IO, CSR, MMIO unitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F04umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3804offcore_response.demand_rfo.any_cache_dramOffcore demand RFO requests satisfied by the IO, CSR, MMIO unitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1880offcore_response.other.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8040offcore_response.pf_ifetch.local_cache_dramoffcore_response.pf_ifetch.remote_cache_dramoffcore_response.pf_rfo.remote_cache_dramAll Floating Point to and from MMX transitionssimd_int_128.packed_arithumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2011offcore_response.any_ifetch.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x20FFoffcore_response.corewb.local_dramOffcore demand data reads satisfied by any DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF801Offcore demand code reads satisfied by the local DRAMoffcore_response.demand_ifetch.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF820L1I Instruction fetchesumask=0x2,period=2000000,event=0x13umask=0x4,period=100000,event=0xb8Mispredicted call branches executedReference cycles when thread is not halted (fixed counter)inv=1,umask=0x0,period=2000000,cmask=2,event=0x3cExecution pipeline restart due to Memory ordering conflictsOther Resource related stall cyclesSIMD Packed-Double Uops retired (Precise Event)umask=0x4,period=2000000,event=0xd1uops_decoded.ms_cycles_activeumask=0x1f,any=1,period=2000000,cmask=1,event=0xb1uops_executed.core_stall_cyclesumask=0x4,any=1,period=2000000,event=0xb1Uops issued on ports 2, 3 or 4inv=1,umask=0x1,period=2000000,cmask=1,event=0xeumask=0x1,period=2000000,event=0xc2dtlb_misses.walk_completedumask=0x1,period=2000000,event=0xaeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040002offcore_response.other.l4_hit_local_l4.any_snoopCounts the number of L2 cache lines filling the L2. Counting does not cover rejectsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001C0002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001C8000offcore_response.other.l4_hit_local_l4.snoop_missperiod=200003,umask=0x4,event=0xf2period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100001period=20011,umask=0x2,event=0xd2period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001C0001offcore_response.demand_rfo.l3_hit_e.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400028000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC01C8000offcore_response.other.l3_hit_s.snoop_noneoffcore_response.demand_rfo.l3_hit_s.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0400002l2_lines_out.useless_prefperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040004period=20011,umask=0x4,event=0xd2Retired load instructions which data sources were HitM responses from shared L3  Supports address when precise (Precise event)offcore_requests.all_requestsoffcore_response.other.l3_hit_e.any_snoopperiod=2000003,umask=0x1,event=0xd1period=2000003,umask=0x8,event=0x60cmask=1,period=2000003,umask=0x8,event=0x79Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymorefrontend_retired.latency_ge_16period=200003,umask=0x4,event=0x83Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)frontend_retired.latency_ge_2_bubbles_ge_3period=100007,umask=0x1,event=0xc6,frontend=0x100206period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204008000offcore_response.demand_code_rd.l3_miss.snoop_non_dramrtm_retired.aborted_timerperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C400004Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQcmask=1,inv=1,period=2000003,umask=0x1,event=0xb1uops_executed.x87other_assists.anyinst_retired.any / mem_inst_retired.all_storesIpFLOPperiod=2000003,umask=0x20,event=0x8Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitectureStores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)period=100003,umask=0x2,event=0x49L2 cache requests from this coreCounts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts any data read (demand & prefetch) that miss L2 with a snoop miss responseCounts any data read (demand & prefetch) that have any response typeCounts any request that hit in the other module where modified copies were found in other core's L1 cacheCounts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructionsJCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to MCounts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REFRetired load uops with locked access. (Precise Event - PEBS) (Precise event)This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event)Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_rfo.llc_hit.snoop_missCounts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts all demand & prefetch prefetch RFOs offcore_response.pf_l_data_rd.any_responseoffcore_response.any_request.llc_miss_local.dramOffcore read requestsoffcore_requests_outstanding.any.read_not_emptyoffcore_requests_outstanding.demand.read_dataoffcore_requests_outstanding.demand.read_data_not_emptyumask=0x4,period=2000000,event=0xf4offcore_response.any_data.local_dram_and_remote_cache_hitoffcore_response.any_request.local_dram_and_remote_cache_hitREQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f77REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATIONREQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff70misalign_mem_ref.storeumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3077umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3003offcore_response.demand_data_rd.other_local_dramREQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAMREQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x2,period=2000000,cmask=1,event=0xb3Mispredicted retired branch instructions (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2708period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010491Counts all demand & prefetch data reads that hit in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0004Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts all prefetch (that bring data to LLC only) RFOs that have any response typeOFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWDperiod=2000003,umask=0x80,event=0xc7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00490Counts all prefetch data reads that miss the L3 and the data is returned from local dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dramoffcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts prefetch (that bring data to L2) data reads that miss in the L3offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x2,event=0xfe(cpu_clk_unhalted.thread / cpu_clk_unhalted.ref_tsc) * msr@tsc@ / 1000000000 / duration_timeIO_Read_BWunc_m_act_count.wrMMIO reads. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x41a33unc_iio_data_req_of_cpu.mem_write.part1Local requests for exclusive ownership of a cache line  without receiving data. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data: Part 0. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 1Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc1unc_iio_txn_req_of_cpu.peer_read.part3event=0x29unc_m2m_directory_update.i2sumask=0x8,event=0x2eBL Egress (to CMS) Occupancy; All. Unit: uncore_m2m unc_upi_rxl0p_power_cyclesoffcore_response.all_data_rd.l3_hit.hit_other_core_fwdoffcore_response.all_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040490offcore_response.all_pf_rfo.l3_hit_f.no_snoop_neededoffcore_response.all_pf_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_reads.l3_hit.snoop_noneoffcore_response.all_reads.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00802007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_m.snoop_noneoffcore_response.all_rfo.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400004offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020002offcore_response.other.l3_hit.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_f.snoop_missoffcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020080offcore_response.pf_l3_data_rd.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020100lsd.uops / (idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000491ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_pf_data_rd.l3_miss_local_dram.snoop_noneOCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDEDOCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARDOCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B8007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000122Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000004ocr.demand_code_rd.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84008000Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000400Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000010ocr.pf_l2_rfo.l3_miss.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdocr.pf_l3_rfo.l3_miss.hit_other_core_fwdocr.pf_l3_rfo.l3_miss.no_snoop_neededocr.pf_l3_rfo.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000100offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITMoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdoffcore_response.demand_rfo.l3_miss_local_dram.hitm_other_coreoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_COREoffcore_response.other.l3_miss_remote_hop1_dram.hitm_other_coreoffcore_response.pf_l1d_and_sw.l3_miss.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwdocr.all_data_rd.l3_hit_f.snoop_missocr.all_data_rd.l3_hit_m.hit_other_core_no_fwdocr.all_data_rd.l3_hit_s.hit_other_core_fwdOCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISSocr.all_data_rd.pmm_hit_local_pmm.snoop_noneOCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwdOCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_COREOCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_f.snoop_missOCR.ALL_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_M.ANY_SNOOPOCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_f.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOPocr.demand_code_rd.l3_hit_f.hit_other_core_fwdocr.demand_code_rd.l3_hit_m.hitm_other_coreocr.demand_code_rd.pmm_hit_local_pmm.snoop_noneocr.demand_rfo.l3_hit.no_snoop_neededCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISSCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOPocr.demand_rfo.supplier_none.any_snoopocr.other.l3_hit.snoop_hit_with_fwdocr.other.l3_hit_e.any_snoopocr.other.l3_hit_f.no_snoop_neededocr.other.l3_hit_m.hitm_other_coreocr.other.l3_hit_m.snoop_missocr.other.supplier_none.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOPocr.pf_l2_data_rd.l3_hit.snoop_noneocr.pf_l2_data_rd.supplier_none.hitm_other_coreCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwdocr.pf_l2_rfo.l3_hit_f.any_snoopocr.pf_l2_rfo.l3_hit_m.snoop_noneCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONECounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_e.snoop_missocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwdocr.pf_l3_data_rd.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwdocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwdIntel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts. Unit: uncore_imc period=1000003,umask=0x1,event=0x48Store Read transactions pending for off-core. Highly correlatedperiod=500009,umask=0x4,event=0x80Cycles when uops are being delivered to IDQ while MS is busy1 - cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_distributedCounts the number of times a TSX line had a cache conflictCounts streaming stores that was not supplied by the L3 cacheCounts hardware prefetch RFOs (which bring data to L2) that have any type of responseocr.streaming_wr.local_dramocr.demand_data_rd.l3_hit.anyperiod=100003,umask=0x8,event=0x32ocr.demand_data_rd.local_dramCounts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical corebr_misp_retired.indirect_callCounts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchperiod=100003,umask=0x2,event=0x8unc_cha_tor_inserts.io_pcirdcur * 64 / 1000000000 / duration_timeunc_cha_tor_inserts.ia_missumask=0xC817FE01,event=0x35TOR Inserts : RFOs issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Occupancy : All requests from iA Cores that Hit the LLC. Unit: uncore_cha CMS Clockticks. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_remoteumask=0xC8977E01,event=0x35umask=0xc86ffe01,event=0x35Number Transactions requested of the CPU : Card reading from DRAM. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part5fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0x83fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0x83unc_iio_txn_req_of_cpu.cmpd.part5Free running counter that increments for IIO clocktick. Unit: uncore_iio fc_mask=0x04,ch_mask=0x20,umask=0x03,event=0xc2unc_m2m_cms_clockticksCounts the number of load uops retired that hit the level 1 data cache  Supports address when precise (Precise event)Counts the number of unhalted core clock cycles. (Fixed event)umask=0xC001FE01,event=0x35,config1=0x40e33btclear.anyperiod=200003,umask=0x1,event=0x63period=200003,umask=0x2,event=0xcbtopdown_fe_bound.cisctopdown_fe_bound.otherCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page faultCounts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervalsbp_l1_btb_correctbp_l1_tlb_fetch_hitThe number of 64 byte instruction cache line fulfilled from system memory or another cachebp_l1_tlb_miss_l2_missumask=0x04,event=0x63umask=0x3f,event=0x9aUnit: uncore_dfpmc This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the schedulerDivide and square root OpsThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_retired_ser_ops.sse_bot_retLS MAB allocates by type - DC prefetcherall_l2_cache_accessesall_l2_cache_missesl2_cache_misses_from_ic_missbp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_missumask=0x02,event=0x94bp_l1_tlb_miss_l2_tlb_miss.if1gTotal number of fp uOpsL1 DTLB Miss. DTLB reload hit a coalesced pagels_pref_instr_dispSoftware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote)Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote)umask=0x02,event=0x5aCycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semanticsLoad-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedls_dmnd_fills_from_sys.mem_io_remoteumask=0x04,event=0x43Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_hw_pf_dc_fills.int_cacheHardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCXde_dis_dispatch_token_stalls2.int_sch3_token_stallumask=0xe8,event=0x60LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODEDC_REFILL_FROM_L2FR_RETIRED_NEAR_RETURNSMEM_UNALIGNED_ACCESS_REPLAYEVENT_34HEVENT_45HEVENT_53HEVENT_92HEVENT_A3HEVENT_E9HEVENT_EDHL1D_CACHE_INVALEXC_TRAP_FIQSTORE_COMPLETEDICACHE_REQUESTSBRANCH_MISPRED_CYCLESL2_CACHE_SINGLE_BIT_ERRORSOCP_ALL_CACHEABLE_REQUESTSUULOADCFETCHINSTR_COMPLETEDL1_DATA_SNOOPSTRUE_BRANCH_TARGET_HITSGPR_ISSUE_QUEUE_DISPATCHESMTSPR_INSTR_COMPLETEDDATA_BKPT_MATCHESSTWCX_INSTR_COMPLETEDTOUCHES_TRANSLATED_ALLOCATED_TO_DLFBDATA_L1_CACHE_CASTOUTSSTASH_REQUESTS_L2L2_COHERENT_LINE_INVALIDATIONSinvcancelledprobe-hitTHRESHOLDQUALIFIERUCPINTEL_CORE2EXTREMETCpme->table[idx].name	%s
LLC-MISS-RHITMbr_misp_retired.all_branchesch_mask%s, "pmcid": "0x%08x", "pid": "%d", "value": "0x%016jx"}
GenuineIntel-6-3Fv2GenuineIntel-6-2EPer-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTuneCore actual clocks when any thread is active on the physical corecpu_clk_unhalted.thread:k / cpu_clk_unhalted.threadl2_rqsts.demand_data_rd_missL1D data line replacementsumask=0x1,cmask=1,period=2000003,event=0x60umask=0x4,cmask=1,period=2000003,event=0x60umask=0x4,period=100003,event=0xb0This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)l2_lines_in.sumask=0x10,period=2000003,event=0xc7umask=0x2a,period=2000005,event=0xc7umask=0x2,period=2000003,event=0x79umask=0x10,cmask=1,period=2000003,event=0x79idq.all_dsb_cycles_4_uopsThis event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQumask=0x2,period=2000003,event=0x54Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock BufferNumber of times an HLE execution aborted due to uncommon conditionshle_retired.aborted_misc3cpl_cycles.ring0umask=0x20,period=2000003,event=0xeCount XClk pulses when this thread is unhalted and the other thread is haltedNumber of integer Move Elimination candidate uops that were eliminatedrs_events.empty_cyclesbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_indirect_jump_non_call_retumask=0x90,period=200003,event=0x88br_inst_exec.all_branchesCycles stalled due to no eligible RS entry availableCycles while L1 cache miss demand load is outstandingumask=0x1,cmask=1,period=2000003,event=0xb1umask=0x40,period=100003,event=0xc1umask=0x2,period=2000003,event=0xc2umask=0x0,period=400009,event=0xc4This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retiredCounts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endumask=0x3,event=0x35,filter_opc=0x192unc_h_requests.reads_localevent=0x86unc_m_power_self_refreshumask=0x8,event=0x2This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu umask=0x40,period=100003,event=0x49Misses in all ITLB levels that cause completed page walks  Spec update: BDM69itlb_misses.stlb_hit_4kumask=0x18,period=2000003,event=0xbcpage_walker_loads.itlb_l1This event counts the number of DTLB flush attempts of the thread-specific entriesFrontend_BoundFLOPcBranch_Misprediction_Cost_SMTAverage data fill bandwidth to the L1 data cache [GB / sec]offcore_response.demand_data_rd.l3_hit.snoop_not_neededoffcore_response.demand_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020004offcore_response.corewb.l3_hit.snoop_hitmCounts prefetch (that bring data to L2) data reads have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020040offcore_response.pf_l2_code_rd.l3_hit.snoop_hitmCounts all prefetch (that bring data to LLC only) data reads have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0122Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementoffcore_response.demand_data_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000100offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C8000offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000240offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000122inv=1,umask=0x1,edge=1,period=200003,cmask=1,event=0x5eumask=0x1,period=2000003,cmask=1,event=0xa3A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor coreUnit: uncore_cbox L3 Lookup any request that access cache and found line in MESI-stateUnit: uncore_arb Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etcAll retired load uops  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00200umask=0x51,period=200000,event=0x29umask=0x4f,period=200000,event=0x2cumask=0x7f,period=200000,event=0x2eumask=0x42,period=200000,event=0x2eumask=0x82,period=2000000,event=0x10umask=0x1,period=2000000,event=0xb3simd_assistmacro_insts.all_decodedNonzero segbase ld-op-st 1 bubblebus_trans_rfo.all_agentsbus_trans_p.all_agentsPartial bus transactionsbus_trans_any.selfext_snoop.this_agent.cleanext_snoop.all_agents.cleanMicro-op reissues for any causeMicro-op reissues for any cause (At Retirement)br_missp_type_retired.returnbr_inst_retired.mispred_not_takenbogus_brumask=0x9,period=200000,event=0x8Number of page-walks executeditlb.missesumask=0x1,period=200003,event=0x51umask=0x83,period=200003,event=0xd0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000432b7umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043010offcore_response.pf_l1_data_rd.l2_miss.anyCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_hitoffcore_response.full_streaming_stores.l2_hitoffcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000010Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise)issue_slots_not_consumed.resource_fullUnfilled issue slots per cycle because of a full resource in the backendissue_slots_not_consumed.recoveryCounts loads that block because their address modulo 4K matches a pending store (Must be precise)Loads blocked (Precise event capable) (Must be precise)MS uops retired (Precise event capable) (Must be precise)Counts far branch instructions retired.  This includes far jump, far call and return, and Interrupt call and return (Must be precise)Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise)Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise)Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cacheoffcore_response.pf_l2_rfo.outstandingCounts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000400Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014800offcore_response.streaming_stores.l2_miss.hitm_other_coreCounts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event (Must be precise)Reference cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counterdtlb_store_misses.walk_pendingtlb_flushes.stlb_anyumask=0x20,period=20003,event=0xbdAll requests that miss L2 cache  Spec update: HSD78Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are eCounts prefetch (that bring data to L2) data reads hit in the L3(Precise event)Speculative cache-line split load uops dispatched to L1DStall cycles due to IQ is fullCycles at least 2 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles no executable uops retired (Precise event)Unit: uncore_cbox An external snoop hits a non-modified line in some processor coreUnit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor coreL3 Lookup external snoop request that access cache and found line in MESI-stateEach cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)Completed page walks due to store misses in one or more TLB levels of 2M/4M page structureoffcore_response.pf_l2_rfo.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00080umask=0x10,period=200003,event=0x24umask=0x80,period=200003,event=0x24umask=0x1,period=200003,event=0x28umask=0x4,period=200003,event=0x28Counts the number of lines brought into the L1 data cacheRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event)umask=0x1,period=2000003,event=0x10umask=0x80,period=2000003,event=0x10Cycles which a Uop is dispatched on port 3Unit: uncore_cbox A snoop misses in some processor coreumask=0x04,event=0x22A snoop hits a non-modified line in some processor coreUnit: uncore_arb This 48-bit fixed counter counts the UCLK cyclesunc_cbo_cache_lookup.esUnit: uncore_cbox LLC lookup request that access cache and found line in E-state or S-stateDemand load cycles page miss handler (PMH) is busy with this walkRemote cache HITMCounts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accessesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00010LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox unc_q_txl0p_power_cyclesNumber of data flits transmitted . Unit: uncore_qpi Write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu freq_ge_3000mhz_cycles %unc_p_freq_ge_4000mhz_transitionsRetired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cachel2_store_lock_rqsts.hit_edsb_fill.all_cancelCycles with at least one slow LEA uop being allocatedMispredicted taken branch instructions retired (Precise event)This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in anInstructions retired. (Precise Event - PEBS) (Must be precise)Counts the number of L2 cache missesmem_uops_retired.utlb_miss_loadsumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000082000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000401000Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010100umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080080offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_foffcore_response.pf_l2_code_rd.l2_hit_near_tile_mCounts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080020Counts demand code reads and prefetch code reads that accounts for any responseoffcore_response.partial_reads.l2_hit_this_tile_mCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000200Counts any request that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000002umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180040Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateCounts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400100umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100403091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080203091Counts Demand cacheable data writes that accounts for data responses from DRAM Farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600070umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800001offcore_response.partial_reads.ddrCounts the number of mispredicted branch instructions retired that were conditional jumps (Precise event)This event counts the number of times that the pipeline stalled due to FP operations needing assistsThis event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retireCounts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entryrecycleq.sta_fullumask=0xf9,period=200003,event=0xc5ddr bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_imc cache_lock_cycles.l1dumask=0x4,period=2000000,event=0x51L1D snoop eviction of cache lines in M stateumask=0x1,period=2000000,event=0x40L1D hardware prefetch requestsL1 writebacks to L2 in E stateumask=0xf,period=100000,event=0x28L2 data prefetches in the I state (misses)l2_transactions.filll2_write.lock.m_stateMemory instructions retired above 4 clocks (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x711Offcore data reads satisfied by a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x144umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2FFoffcore_response.any_request.local_cacheOffcore RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_rfo.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF77umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF33umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4733offcore_response.data_in.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F03umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF04Offcore demand code reads satisfied by a remote cacheOffcore demand RFO requests satisfied by the LLCOffcore prefetch data requests satisfied by a remote cache or remote DRAMoffcore_response.pf_data.remote_cache_hitmoffcore_response.pf_data_rd.llc_hit_other_core_hitmOffcore prefetch code reads satisfied by the LLC and HIT in a sibling coreOffcore prefetch RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.prefetch.local_cacheumask=0x4,period=20000,event=0xf7umask=0x2,period=2000000,event=0xccsimd_int_64.packOffcore code reads satisfied by any DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF844Offcore writebacks to a remote DRAMoffcore_response.pf_data.local_dramOffcore prefetch RFO requests satisfied by a remote DRAMbpu_clears.laterat_stalls.flagsumask=0x7,period=200000,event=0x4Indirect return branches executedRetired conditional branch instructions (Precise Event)umask=0x4,period=2000,event=0x89umask=0x7,period=20000,event=0x89umask=0x2,period=20000,event=0xc3uops_executed.port234_coreumask=0x2,period=200000,event=0x8offcore_response.demand_rfo.l3_hit.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040040002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100004offcore_response.demand_rfo.l4_hit_local_l4.snoop_noneCounts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTSoffcore_response.demand_data_rd.l3_hit_m.spl_hitmem_load_l3_hit_retired.xsnp_noneoffcore_response.other.l4_hit_local_l4.snoop_nonecmask=6,period=2000003,umask=0x1,event=0x60period=2000003,umask=0x8,event=0xc7period=100007,umask=0x1,event=0xc6,frontend=0x14Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3offcore_response.demand_code_rd.l3_hit_e.snoop_non_dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C400001offcore_requests_outstanding.l3_miss_demand_data_rdoffcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dramNumber of times we entered an HLE region. Does not count nested transactionsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC4000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C408000Number of instructions retired. General Counter - architectural event  Spec update: SKL091, SKL044period=2000003,umask=0x1,event=0xc0Not taken branch instructions retired  Spec update: SKL091( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single ) / cyclesAverage per-core data access bandwidth to the L3 cache [GB / sec]OSCounts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completedCounts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a faultperiod=100003,umask=0x8,event=0x49umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008008Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredictedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0200This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more informationCounts all prefetch data reads that miss the LLC  and the data returned from dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400040offcore_response.pf_llc_rfo.llc_miss.dramumask=0x8,period=100000,event=0xb0offcore_requests.any.rfoOutstanding offcore readsREQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHEREQUEST = ANY RFO and RESPONSE = LOCAL_CACHEREQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff33REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5050REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIToffcore_response.pf_ifetch.all_local_dram_and_remote_cache_hitREQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISSoffcore_response.any_request.other_local_dramREQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IN and RESPONSE = ANY_LLC_MISSREQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = OTHER and RESPONSE = ANY_LLC_MISSoffcore_response.prefetch.any_dram_and_remote_fwddtlb_misses.walk_cyclesumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5840period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0002Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0020fp_arith_inst_retired.512b_packed_doubleperiod=2000003,umask=0x40,event=0xc7Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dramCounts all demand code reads that miss the L3 and the data is returned from local dramoffcore_response.pf_l3_rfo.l3_miss.any_snoopRate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)unc_m_cas_count.allevent=0x81uncore_upi llfc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x83unc_cha_misc.rfo_hit_sumask=0x01,event=0x13Read request for 4 bytes made by the CPU to IIO Part2. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc1Write request of up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio uncore_irpPCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline. Unit: uncore_irp Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the meshunc_m2m_directory_lookup.state_sCounts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid)unc_m2m_prefcam_insertsumask=0x03,event=0x15Clocks of the Intel Ultra Path Interconnect (UPI). Unit: uncore_upi ll Protocol header and credit FLITs transmitted across any slot. Unit: uncore_upi ll mem_load_retired.local_pmmThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800807F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800407F7offcore_response.all_reads.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0004This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONEoffcore_response.demand_rfo.l3_hit_e.hit_other_core_fwdoffcore_response.demand_rfo.l3_hit_s.hitm_other_coreoffcore_response.other.l3_hit_s.no_snoop_neededoffcore_response.other.pmm_hit_local_pmm.snoop_noneoffcore_response.pf_l1d_and_sw.l3_hit.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100010offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_m.snoop_noneoffcore_response.pf_l3_rfo.l3_hit_s.snoop_noneMEM_PMM_Read_Latencyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000491ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdOCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000490ocr.all_pf_rfo.l3_miss.any_snoopocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwdOCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04040007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000122OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDEDCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONEocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoopCounts any other requests OCR.OTHER.L3_MISS.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110008000ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000010ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l3_rfo.l3_miss.any_snoopocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwdocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.all_data_rd.l3_miss_local_dram.hitm_other_coreoffcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_neededoffcore_response.all_reads.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.all_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.other.l3_miss_local_dram.hitm_other_coreoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREOCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDOCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDOCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISSocr.all_reads.l3_hit_f.hit_other_core_no_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOPocr.demand_data_rd.l3_hit.hit_other_core_no_fwdocr.demand_rfo.pmm_hit_local_pmm.any_snoopCounts any other requests  OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.any_responseocr.pf_l1d_and_sw.l3_hit_m.hitm_other_coreocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwdocr.pf_l2_data_rd.any_responseocr.pf_l2_data_rd.l3_hit_e.hitm_other_coreocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwdocr.pf_l2_data_rd.supplier_none.snoop_missCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_e.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l3_rfo.l3_hit_m.snoop_noneocr.pf_l3_rfo.l3_hit_s.any_snoopocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_noneunc_m_pmm_bandwidth.readunc_m_pmm_cmd1.wrunc_m_pmm_wpq_occupancy.allAll Clean line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc umask=0x04,event=0x2cperiod=100003,umask=0x1,event=0x51period=1000003,umask=0x81,event=0xd0Demand Data Read transactions pending for off-core. Highly correlatedCounts the number of demand Data Read requests initiated by load instructions that hit L2 cachesq_misc.sq_fullRetired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event)Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fillcmask=5,period=2000003,umask=0x4,event=0x79Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalledUops not delivered by IDQ when backend of the machine is not stalledperiod=100003,umask=0x8,event=0x54Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatchperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00004ocr.hwpf_l1d_and_swpf.l3_hit.anyocr.hwpf_l2_data_rd.any_responseCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent or notCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedAll indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch) (Precise event)cmask=1,inv=1,period=1000003,umask=0x2,event=0xc2inst_retired.stall_cyclescmask=4,period=1000003,umask=0x4,event=0xa3Number of uops executed on port 0This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthreadAll mispredicted branch instructions retired (Precise event)Page walks completed due to a demand data store to a 4K pageumask=0x01,event=0xe0umask=0xC001FD01,event=0x36umask=0xC88FFD01,event=0x35TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_clflushTOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC. Unit: uncore_cha fc_mask=0x07,ch_mask=0x04,umask=0x80,event=0x83fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0xc0unc_iio_data_req_of_cpu.mem_read.part6Clockticks of the IO coherency tracker (IRP). Unit: uncore_irp unc_i_faf_fullevent=0x16unc_m2m_tag_hit.nm_rd_hit_cleanunc_m2p_cms_clockticksPrecharge due to read on page miss, write on page miss or PGT. Unit: uncore_imc period=200003,umask=0x10,event=0xd164 * longest_lat_cache.miss / 1000000000 Counts the number of BACLEARS due to a conditional jumpThis event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKSThis event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HITtopdown_fe_bound.decodeperiod=200003,umask=0xfe,event=0xc4Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event)Indirect Branch Prediction for potential multi-target branch (speculative)event=0x94ic_fetch_stall.ic_stall_back_pressurebp_tlb_relMiscellaneous events covered in more detail by l2_request_g2 (PMCx061)l2_request_g2.ic_rd_sizedumask=0x01,event=0x64umask=0xff,event=0x70All L3 Miss Request Types. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc Add/subtract OpsThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPSumask=0x20,event=0x3This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPSumask=0x04,event=0x3umask=0x04,event=0x4umask=0x02,event=0x5ls_dispatch.ld_st_dispatchTotal Page Table Walks on I-sideumask=0x10,event=0xafl2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)fp_ret_sse_avx_ops.mac_flopsls_locks.spec_lock_hi_specumask=0x08,event=0x59umask=0x80,event=0xaeumask=0x20,event=0xaeumask=0x04,event=0x28fDemand Data Cache Fills by Data Source. From cache of different CCX in same nodels_any_fills_from_sys.mem_io_localumask=0x04,event=0x44Any Data Cache Fills by Data Source. From Local L2 to the corels_sw_pf_dc_fills.lcl_l2Any Integer dispatch. Types of Oops Dispatched from DecoderL1 Data Cache Fills: From Memory,IC_L1_ITLB_MISS_AND_L2_ITLB_MISSFR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIETEVENT_29HEVENT_6EHEVENT_90HEVENT_ACHEVENT_FDHEVENT_FEHL1D_CACHE_WBL1D_CACHE_REFILL_LDASE_SPECBR_IMMED_SPECL3D_CACHE_ALLOCATECYCLETAGCACHE_READ_HITRETURNISPRAM_STALL_CYCLESFSB_LT_QUARTERDUAL_ISSUE_CYCLESVFPU_INSTR_COMPLETEDLSU_LMQ_FULL_STALLFP_ONE_HALF_FPSCR_RENAMES_BUSYCOMPLETION_QUEUE_ENTRIES_OVER_THRESHOLDTHIRD_SPECULATION_BUFFER_ACTIVEL3_CACHE_CASTOUTSCYCLES_IN_SUPERONE_PLUS_INSTR_COMPLETEDCYCLES_IDLETOTAL_ALLOCATED_TO_DLFBFPU_RESULT_STALL_CYCLESUNKNOWNLLC_MISSES{"type": "procfork"v9GenuineIntel-6-6CDSB; Frontend_Bandwidth( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cpu_clk_unhalted.thread(cstate_pkg@c7\-residency@ / msr@tsc@) * 100l2_rqsts.all_demand_data_rdThis event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point  Spec update: BDM76offcore_requests_outstanding.demand_code_rdOffcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76umask=0x2,period=2000003,event=0x63umask=0x21,period=100007,event=0xd0This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)umask=0x8,period=100003,event=0xd1Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)umask=0x1,period=100007,event=0xd3floating pointThis event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable  Spec update: BDM30This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalidCycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathThis event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQidq.all_mite_cycles_4_uopsumask=0x1,cmask=1,period=2000003,event=0x9cdsb2mite_switches.penalty_cyclestx_mem.abort_hle_elision_buffer_mismatchtx_exec.misc4umask=0x4,period=2000003,event=0xc8Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)Loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)ld_blocks.no_srCore cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the threadmove_elimination.simd_eliminatedTaken speculative and retired direct near callsSpeculative and retired mispredicted macro conditional branchesMicro-op dispatches cancelled due to insufficient SIMD physical register file read portsCycles per core when uops are exectuted in port 1This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7resource_stalls.sbThis event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front endCounts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem)cycle_activity.cycles_mem_anyCycles where at least 2 uops were executed per-threaduops_executed.core_cycles_ge_3uops_retired.stall_cyclesNumber of machine clears (nukes) of any typeumask=0x20,period=100003,event=0xc3This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: BDW98 (Must be precise)Taken branch instructions retired. (Precise Event - PEBS) (Precise event)This event counts all mispredicted macro branch instructions retiredunc_c_clockticksumask=0x1,event=0x35,filter_opc=0x180,filter_tid=0x3eL2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x8,event=0x1Shared line forwarded from remote cache. Unit: uncore_ha freq_trans_cycles %Load miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69dtlb_store_misses.walk_completedStore misses that miss the  DTLB and hit the STLB (2M)Number of DTLB page walker hits in Memory  Spec update: BDM69, BDM98umask=0x21,period=2000003,event=0xbcThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retiredInstructions per Store (lower number means higher occurance rate)umask=0xc4,period=200003,event=0x24umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0010offcore_response.pf_l2_rfo.supplier_none.any_snoopoffcore_response.pf_l2_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010080offcore_response.pf_l3_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020100offcore_response.pf_l3_code_rd.supplier_none.any_snoopoffcore_response.all_pf_data_rd.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020090offcore_response.all_pf_rfo.supplier_none.snoop_noneoffcore_response.all_pf_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020240offcore_response.all_pf_code_rd.l3_hit.snoop_noneCounts all demand & prefetch RFOsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020122input - Invalid Operation, Denormal Operand, SNaN Operand  (Precise Event)umask=0x24,period=2000003,cmask=4,event=0x79This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. 
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cyclesoffcore_response.demand_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000008offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000020offcore_response.pf_l3_rfo.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000200offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwdoffcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000240offcore_response.all_rfo.l3_miss.snoop_noneA cross-core snoop resulted from L3 Eviction which misses in some processor coreUnit: uncore_cbox L3 Lookup write request that access cache and found line in M-stateunc_cbo_cache_lookup.any_iRetired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0244Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_data_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC007F7offcore_response.all_reads.llc_miss.local_dramumask=0x4f,period=200000,event=0x2bumask=0x41,period=200000,event=0x2dl2_rqsts.self.prefetch.s_statel2_reject_busq.self.prefetch.s_stateumask=0x1,period=10000,event=0x11umask=0x0,period=2000000,event=0xb1SIMD Instructions retiredthermal_tripumask=0xc0,period=200000,event=0x3bumask=0x40,period=200000,event=0x63umask=0x40,period=200000,event=0x65bus_trans_inval.all_agentsumask=0x40,period=200000,event=0x6aDeferred bus transactionsext_snoop.this_agent.hitmHIT signal assertedumask=0x20,period=200000,event=0x7bHITM signal assertedcpu_clk_unhalted.busumask=0x0,period=2000000,event=0xc4reissue.overlap_store.arumask=0x5,period=200000,event=0x8ITLB flushesumask=0x2,period=200003,event=0x86Store uops retired (Precise event capable)  Supports address when precise (Must be precise)mem_load_uops_retired.dram_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000032b7offcore_response.any_rfo.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600001000offcore_response.corewb.l2_miss.anyoffcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_neededCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040001Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clearumask=0x1,period=200003,event=0xe9Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise)Machine clears due to memory ordering issueumask=0x1,period=200003,event=0x86Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY)uops_not_delivered.anyInstructions retired (Precise event capable) (Must be precise)uops_retired.msumask=0x11,period=200003,event=0xd0dl1.replacementCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystemumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000008offcore_response.bus_locks.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000400Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cacheRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Spec update: HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwdThis event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequentlyumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400244offcore_response.pf_l2_rfo.l3_miss.any_responseoffcore_response.demand_code_rd.l3_miss.any_responseuops_issued.core_stall_cyclesCycles with pending memory loads. Set Cmask=2 to count cycleThis event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data)Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: HSD140 (Must be precise)Completed page walks due to demand load misses that caused 4K page walks in any TLB levelsdtlb_store_misses.pde_cache_missumask=0x80,period=100003,event=0x49Counts the number of Extended Page Table walks from the DTLB that hit in memoryNumber of X87 FP assists due to input valuesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400122umask=0xf,period=200003,event=0x27Retired load uops which data sources following L1 data-cache miss (Precise event)Counts number of X87 uops executedNumber of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operationsLoads blocked by overlapping with store buffer that cannot be forwardedReference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)Cycles which a Uop is dispatched on port 1Cycles per core when uops are dispatched to port 1Uops dispatched to port 2, loads and stores per core (speculative and retired)Retired uops (Precise event)umask=0x02,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in S-stateCompleted page walks in ITLB due to STLB load misses for large pagesoffcore_response.demand_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f8203f7Counts all prefetch (that bring data to LLC only) code reads that miss in the LLCPartial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial. Unit: uncore_cbox umask=0x8A,event=0x36event=0x60unc_p_freq_ge_1200mhz_cyclesevent=0xd,edge=1,filter_band2=30event=0xe,edge=1,filter_band3=40This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more informationdsb_fill.other_cancelcycle_activity.cycles_no_dispatchresource_stalls.lb_sbpartial_rat_stalls.flags_merge_uop_cycles(unc_c_tor_occupancy.miss_all / unc_c_clockticks) * 100.Load misses at all DTLB levels that cause completed page walksCounts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000832f7offcore_response.any_code_rd.l2_hit_near_tile_e_fCounts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_data_rd.l2_hit_near_tile_mCounts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_software.l2_hit_near_tile_mCounts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.partial_reads.outstandingCounts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_rfo.l2_hit_near_tile_e_foffcore_response.demand_data_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080001Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in M stateCounts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004008000Counts any Read request  that accounts for responses which hit its own tile's L2 with data in S stateCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in F stateCounts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_rfo.l2_hit_near_tileCounts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_pf_l2.l2_hit_near_tileCounts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_data_rd.mcdram_farCounts any request that accounts for data responses from DRAM LocalCounts L2 code HW prefetches that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000020umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600100Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)offcore_response.demand_code_rd.ddrThis event counts the number of micro-ops retired that were supplied from MSROMCounts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocationumask=0x02,event=0x3unc_e_rpq_insertsCycles L1D lockedl1d_all_ref.cacheableL1 data cache load locks in S stateL2 data prefetches in the S stateumask=0x3,period=200000,event=0x24l2_rqsts.prefetchesumask=0x40,period=200000,event=0xf0L2 demand store RFOs in S stateLoad instructions retired remote cache HIT data source (Precise Event)mem_inst_retired.latency_above_threshold_128umask=0x10,period=500,event=0xb,ldlat=0x100mem_inst_retired.latency_above_threshold_64offcore_response.any_data.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF22umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1008Offcore demand data requests satisfied by the LLCOffcore demand data reads satisfied by the LLC or local DRAMoffcore_response.demand_data_rd.remote_cache_hitOffcore demand RFO requests satisfied by a remote cache or remote DRAMOffcore other requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_ifetch.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x440Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x740offcore_response.pf_rfo.llc_hit_no_other_coreOffcore prefetch RFO requests that HIT in a remote cacheOffcore prefetch requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.prefetch.remote_cache_hitumask=0x4,period=2000000,event=0x10offcore_response.any_ifetch.any_dramoffcore_response.any_rfo.any_dramOffcore request = all data, response = any DRAMoffcore_response.demand_data.local_dramOffcore demand data requests satisfied by a remote DRAMoffcore_response.demand_ifetch.any_dramOffcore prefetch code reads satisfied by any DRAMOffcore prefetch RFO requests that missed the LLCumask=0x1,period=2000000,event=0xd2Unconditional call branches executedIndirect call branches executedumask=0x40,period=200000,event=0x88Mispredicted indirect call branches executedbr_misp_exec.return_nearCycles instructions are written to the instruction queueresource_stalls.storeStore buffer stall cyclesUop unfusions due to FP exceptionsuops_executed.port0uops_executed.port015DTLB first level misses but second level hitCounts retired load instructions with at least one uop that hit in the L3 cache  Supports address when precise (Precise event)offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_neededmem_load_retired.l3_missoffcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040001period=100003,umask=0x8,event=0xd1period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040100002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040004Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040020004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001C0002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0108000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00401C0001period=2000003,umask=0x10,event=0xc7Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x400406cmask=4,period=2000003,umask=0x24,event=0x79period=200003,umask=0x2,event=0x83period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000088000offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C400002period=2000003,umask=0x8,event=0x5dperiod=2000003,umask=0x4,event=0x5dperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000002offcore_response.other.l4_hit_local_l4.snoop_non_dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x203C408000period=2000003,umask=0x40,event=0xc8offcore_response.demand_rfo.l3_miss.any_snoopNumber of PREFETCHW instructions executedperiod=2000003,umask=0x1,event=0x32cmask=10,inv=1,period=2000003,umask=0x2,event=0xc2period=2000003,umask=0x4,event=0xa1period=2000003,umask=0x10,event=0xa1period=100003,umask=0x2,event=0x3partial_rat_stalls.scoreboardcmask=4,period=2000003,umask=0x1,event=0xb1period=400009,umask=0x20,event=0xc5Number of cycles using always true condition applied to  PEBS instructions retired event  Spec update: SKL091, SKL044 (Must be precise)Uops inserted at issue-stage in order to preserve upper bits of vector registerscmask=1,edge=1,period=100007,event=0x3cCounts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not emptyperiod=2000003,umask=0x80,event=0xdCounts all (macro) branch instructions retired  Spec update: SKL0911000 * mem_load_retired.l1_miss / inst_retired.any( ( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single ) / 1000000000 ) / duration_timeFLOPS;HPCLoads that miss the DTLB and hit the STLBperiod=100003,umask=0xe,event=0x49Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a faultCounts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)This event counts the number of retired stores that are delayed because there is not a store address buffer availableLoads missed L2 (Precise event)Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch RFOs that miss L2Instruction fetches from IcacheCounts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to timeCounts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0040Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITMoffcore_response.pf_l_ifetch.any_responseoffcore_requests.any.readumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff44REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITMREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PREFETCH and RESPONSE = LOCAL_CACHEoffcore_response.pf_data.other_local_drammem_uncore_retired.remote_hitmperiod=100007,umask=0x8,event=0xd3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0004offcore_response.demand_data_rd.l3_hit.no_snoop_neededoffcore_response.demand_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00490Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cacheCounts all prefetch data reads that miss the L3 and the data is returned from local or remote dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00002offcore_response.pf_l1d_and_sw.l3_miss.remote_hitmoffcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single ) / ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * core_clks )CacheMissesunc_m_rpq_insertsumask=0x01,event=0x59umask=0x04,event=0x3dumask=0x40,event=0x5cRspI Snoop Responses Received. Unit: uncore_cha umask=0x20,event=0x5cumask=0x10,event=0x5cPCIe Completion Buffer occupancy of completions with data: Part 3. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc0unc_iio_data_req_by_cpu.peer_write.part1fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc0fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x83unc_iio_data_req_of_cpu.peer_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x84Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio umask=0x4,event=0xfCounts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not takenunc_m2m_directory_lookup.state_aumask=0x8,event=0x2dMulti-socket cacheline Directory update from I to S. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priorityData Response packets that go direct to Intel UPI. Unit: uncore_upi ll Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA Null FLITs transmitted from any slot. Unit: uncore_upi ll This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020491offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040490offcore_response.all_pf_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200120offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020120offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01002007F7offcore_response.all_reads.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00804007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020122offcore_response.demand_code_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSEoffcore_response.other.l3_hit.snoop_hit_with_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSEoffcore_response.pf_l1d_and_sw.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080080offcore_response.pf_l3_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100100OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000490ocr.all_pf_data_rd.l3_miss.hit_other_core_fwdOCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss.no_snoop_neededOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02100007F7ocr.all_rfo.l3_miss.any_snoopOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000122ocr.demand_code_rd.l3_miss_local_dram.no_snoop_neededocr.demand_data_rd.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_rfo.l3_miss.remote_hit_forwardCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.other.l3_miss.remote_hitmocr.other.l3_miss_local_dram.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requestsocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000010ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOPoffcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwdoffcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwdoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwdoffcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_coreoffcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_coreocr.all_data_rd.any_responseocr.all_pf_data_rd.l3_hit.hitm_other_coreocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwdocr.all_pf_data_rd.l3_hit_m.any_snoopOCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOPOCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISSOCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit.any_snoopOCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDEDOCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISSocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwdOCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISSocr.all_pf_rfo.l3_hit_f.hitm_other_coreOCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_COREOCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit.hit_other_core_no_fwdocr.all_reads.l3_hit.snoop_hit_with_fwdocr.all_reads.pmm_hit_local_pmm.any_snoopOCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_COREOCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDOCR.ALL_RFO.L3_HIT_E.SNOOP_MISSOCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_f.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.pmm_hit_local_pmm.snoop_noneocr.demand_rfo.any_responseocr.demand_rfo.l3_hit_e.hit_other_core_fwdocr.other.l3_hit_m.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwdocr.pf_l1d_and_sw.l3_hit_e.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_e.snoop_missCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_s.snoop_missocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoopocr.pf_l2_data_rd.l3_hit_f.snoop_missCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_f.snoop_missocr.pf_l3_data_rd.l3_hit_s.hitm_other_coreocr.pf_l3_rfo.l3_hit_f.snoop_missCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOPocr.pf_l3_rfo.l3_hit_s.snoop_missocr.pf_l3_rfo.supplier_none.any_snoopperiod=1000003,umask=0x1,event=0xd1Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularityperiod=100007,umask=0x1,event=0xc6,frontend=0x500806cmask=5,period=2000003,umask=0x8,event=0x79period=100003,umask=0x40,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00800Counts the number of times we entered an HLE region. Does not count nested transactionsCounts the number of times a TSX Abort was triggered due to a non-release/commit store to lockCounts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the requestocr.streaming_wr.dramCounts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the requestocr.demand_code_rd.dramocr.hwpf_l1d_and_swpf.any_responseNumber of uops executed on port 4 and 9uops_dispatched.port_6period=500009,umask=0x1,event=0x87Counts cycles when at least 2 micro-ops are executed from any thread on physical coreCounts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other eventsCounts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8period=50021,event=0xc5Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) requestumask=0x02,event=0xd3unc_m_dram_refresh.highunc_m_pre_count.allunc_cha_requests.writes_remoteumask=0xC80FFE01,event=0x35TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC. Unit: uncore_cha TOR Occupancy : All requests from IO Devices that hit the LLC. Unit: uncore_cha umask=0xC897FD01,event=0x35umask=0xC8178A01,event=0x35umask=0xC8178601,event=0x36unc_cha_llc_lookup.data_readNumber Transactions requested of the CPU : CmpD - device sending completion to CPU request. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_write.part5unc_iio_data_req_of_cpu.mem_write.part6unc_iio_txn_req_by_cpu.mem_read.part6unc_iio_comp_buf_inserts.cmpd.part6PCIe Completion Buffer Occupancy of completions with data : Part 6. Unit: uncore_iio unc_i_irp_all.inbound_insertsCounts the number of load uops retired that miss in the level 3 cache (Precise event)TOR Inserts; DRd Opt Pref misses from local IA. Unit: uncore_cha Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basismem_bound_stalls.ifetch_l2_hitCounts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locksCounts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled)period=1000003,umask=0x40,event=0x74period=200003,umask=0xfe,event=0xc5period=2000003,umask=0x2,event=0period=2000003,umask=0x2,event=0x49ept.epde_missperiod=2000003,umask=0x80,event=0x85Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M pageCounts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page faultperiod=200003,umask=0x10,event=0x85The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)umask=0x04,event=0x87l2_request_g1.prefetch_l2_cmdCore to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2L3 cache misses. Unit: uncore_l3pmc Retired Branch Instructions Mispredictedumask=0x80,event=0All FLOPSL1 DTLB Miss of a page of 2M sizels_l1_d_tlb_miss.tlb_reload_32k_l2_missL1 DTLB Reload of a page of 2M sizels_tablewalker.dc_type0Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailableumask=0x02,event=0xafl2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15Floating Point Dispatch Faults. YMM fill faultFloating Point Dispatch Faults. x87 fill faultls_locks.spec_lock_lo_specRetired lock instructions. Low speculative cacheable lock speculation succeededNumber of retired CPUID instructionsNumber of reads of the TSC (RDTSC instructions). The count is speculativeumask=0x08,event=0x43Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die.  From DRAM (home node local)Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local)The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size)All L1 DTLB Misses or Reloads. Use l1_dtlb_misses insteadumask=0x02,event=0x47ls_sw_pf_dc_fills.ext_cache_remotede_dis_dispatch_token_stalls1.store_queue_rsrc_stallde_dis_dispatch_token_stalls2.agsq_token_stallL2 Cache Hits from L2 Cache HWPFl3_cache_accessesLS_SEGMENT_REGISTER_LOADFR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDINGBUS_ACCESSOPS_ISSUEDEVENT_07HEVENT_14HEVENT_3BHEVENT_9EHEVENT_A5HEVENT_BCHEVENT_DDHL2D_CACHE_INVALRC_LD_SPECMEM_CAP_READBRANCH_MISPREDITLB_ACCESSBASE_MISPRED_STALLSCP1_CP2_LOAD_INSNSMISPREDICTED_BRANCH_INSNSLOAD_INSNSRETUSTORECYCLES_NO_COMPLETED_INSTRSDTLB_HW_SEARCH_CYCLES_OVER_THRESHOLDINSTR_BKPT_MATCHESLSU_LMQ_INDEX_ALIASLSU_MISALIGN_STALLCYCLES_WAITING_FROM_L1_INSTR_CACHE_MISSL1_DATA_LOAD_ACCESS_MISSL1_DATA_LOAD_MISS_CYCLESTHIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYL3_CACHE_MISSESBUS_READS_NOT_RETRIEDSNOOP_REQUESTSGCT_EMPTYL3_LOAD_MISSLOAD_NO_REAL_ADDRCYCLES_WITH_INSTRS_DISPATCHEDINSTR_FETCHEDUOPS_DECODEDCYCLES_ISSUE_STALLEDCACHE_INHIBITED_ACCESS_TRANSLATEDSTASH_BUSY_1STASH_BUSY_2L2_CACHE_DIRTY_DATA_ALLOCATIONSDVT0_DETECTEDmultiply-pipe-junk-opsfscycles-to-completetlb-reloadK7K8SCPMUDEBUGperiod{"type": "thr_create"%s, "oldpid": "%d", "newpid": "%d"}
TopDownL14*( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cyclesInstruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)umask=0x42,period=200003,event=0x24umask=0x50,period=200003,event=0x24This event counts the total number of L2 code requestsThis event counts the total number of requests from the L2 hardware prefetchersOffcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM35 (Precise event)Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops with L2 cache misses as data sources. Uses PEBS  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)other_assists.avx_to_ssefp_arith_inst_retired.256b_packed_singleidq.ms_dsb_uopsThis event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQCycles Decode Stream Buffer (DSB) is delivering any UopThis event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)umask=0x30,period=2000003,event=0x79edge=1,umask=0x30,cmask=1,period=2000003,event=0x79Speculative cache line split load uops dispatched to L1 cacheumask=0x8,period=2000003,event=0x5dCounts the number of machine clears due to memory order conflictsumask=0x20,period=2000003,event=0xc8umask=0x10,period=2000003,event=0xc9Number of times a RTM caused a faultmem_trans_retired.load_latency_gt_64umask=0x2,period=2000003,event=0x5cCore cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)cpu_clk_thread_unhalted.ref_xclk_anycpu_clk_unhalted.ref_xclkumask=0x1,period=2000003,event=0x5eThis event counts taken speculative and retired indirect branches that have a return mnemonicThis event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more informationuops_executed_port.port_5_coreThis event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6uops_dispatched_port.port_7umask=0x1,period=2000003,event=0xc2umask=0x3,event=0x35,filter_opc=0x19eLLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x1,event=0x1umask=0xC,event=0x4power_state_occupancy.cores_c0 %This is an occupancy event that tracks the number of cores that are in C6.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events . Unit: uncore_pcu event=0x74umask=0x1,period=100003,event=0x8Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size  Spec update: BDM69Store misses in all DTLB levels that cause completed page walks (2M/4M)  Spec update: BDM69umask=0xe,period=100003,event=0x85Bad_SpeculationCoreIPC_SMTRetired load uops with L2 cache hits as data sources. (Precise Event - PEBS)  Spec update: BDM35.  Supports address when precise (Precise event)offcore_response.demand_code_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0010Counts all prefetch (that bring data to L2) RFOs have any response typeoffcore_response.pf_l2_rfo.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020040offcore_response.pf_l3_data_rd.l3_hit.snoop_noneoffcore_response.pf_l3_code_rd.l3_hit.snoop_missCounts any other requestsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C8000offcore_response.all_pf_data_rd.supplier_none.snoop_missoffcore_response.all_pf_data_rd.l3_hit.snoop_missoffcore_response.all_rfo.l3_hit.snoop_missoffcore_response.demand_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000004offcore_response.corewb.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000010offcore_response.pf_l2_rfo.l3_hit.snoop_non_dramoffcore_response.pf_l2_rfo.l3_miss.snoop_noneoffcore_response.pf_l2_code_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000200offcore_response.all_pf_data_rd.supplier_none.snoop_non_dramoffcore_response.all_pf_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000120offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000122inv=1,umask=0x1,period=2000003,cmask=10,event=0xc2Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetchesSocket_CLKSThis event counts retired load uops which data sources were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event)Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00244Return instructions retired (Precise event)This event counts taken branch instructions retired (Precise event)number of near branch instructions retired that were mispredicted and taken (Precise event)l2_m_lines_in.selfl2_lock.self.e_statel2_ld_ifetch.self.s_stateumask=0x2,period=2000000,event=0x10SIMD unpacked micro-ops executedRetired computational Streaming SIMD Extensions (SSE) scalar-single instructionsumask=0x2,period=2000000,event=0x87umask=0xa,period=200000,event=0x5Memory cluster signals to block micro-op dispatch for any reasoneist_transumask=0xe0,period=200000,event=0x60Bus cycles while processor receives dataBurst read bus transactionsumask=0x40,period=200000,event=0x66bus_trans_inval.selfbus_trans_p.selfCycles during which interrupts are disabledmul.arBus cycles when core is not haltedumask=0x20,period=2000000,event=0x88umask=0x3,period=2000000,event=0xcL2 cache request missesCounts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache.  Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache.  If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data.  When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs  Supports address when precise (Must be precise)Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response  Supports address when precise (Must be precise)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008000offcore_response.partial_streaming_stores.l2_miss.hitm_other_coreCounts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000004umask=0x4,period=200003,event=0x13Core cycles when core is not halted  (Fixed event)Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise)br_misp_retired.jccumask=0x2,period=200003,event=0x5Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000004800Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.outstandingCounts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredPage walks outstanding due to an instruction fetch every cycleCounts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksCounts all L2 store RFO requestsRetired load uops with L2 cache hits as data sources  Spec update: HSD76, HSD29, HSM30.  Supports address when precise (Precise event)Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMXNumber of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroRandomly selected loads with latency value being above 256  Spec update: HSD76, HSD25, HSM26 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00244umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00001Number of multiply packed/scalar single precision uops allocatedinv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xc2This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequentlyunc_cbo_xsnp_response.hit_externalunc_cbo_xsnp_response.hit_evictionNumber of ITLB page walker loads that hit in the L2page_walker_loads.ept_dtlb_memorypage_walker_loads.ept_itlb_l2Count number of STLB flush attemptsThis is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handlingumask=0x4,period=200003,event=0x24umask=0xc,period=200003,event=0x24RFOs that access cache lines in any stateRetired load uops with locked access. (Precise Event)Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0122umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0004Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts number of SSE* or AVX-128 double precision FP scalar uops executedCounts cycles the IDQ is emptySpeculative cache-line split Store-address uops dispatched to L1DLoads with latency value being above 8 (Must be precise)umask=0x08,event=0x22A snoop invalidates a modified line in some processor coreumask=0x20,event=0x22Unit: uncore_cbox LLC lookup request that access cache and found line in M-statemem_load_uops_llc_miss_retired.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0080Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dramMemory controller clock ticks. Use to generate percentages for memory controller CYCLES events. Unit: uncore_imc event=0xd,edge=1Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)umask=0x10,period=100003,event=0x8Counts the number of load micro-ops retired that caused micro TLB missoffcore_response.any_pf_l2.any_responseCounts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800083091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_software.any_responseCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080040umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400020umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080004Counts demand cacheable data and L1 prefetch data reads that accounts for any responseoffcore_response.demand_code_rd.l2_hit_this_tile_moffcore_response.pf_l2_code_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000100Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E stateCounts any request that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_l2_code_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000070Counts UC code reads (valid only for Outstanding response type)  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800408000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400022umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000022Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200080Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactionsCounts Demand cacheable data writes that accounts for data responses from MCDRAM LocalCounts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far)Counts any request that accounts for responses from MCDRAM (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800020Counts all the retired locked loads. It does not include stores because we would double count if we count storesCounts the number of mispredicted near CALL branch instructions retired (Precise event)l1d_cache_ld.i_stateumask=0x4,period=2000000,event=0x41l2_data_rqsts.demand.e_stateumask=0x10,period=200000,event=0x24umask=0x1,period=200000,event=0x24l2_rqsts.prefetch_hitumask=0x4,period=200000,event=0x24L2 writeback to LLC transactionsumask=0x8,period=20000,event=0xfumask=0x10,period=20,event=0xb,ldlat=0x1000mem_inst_retired.latency_above_threshold_8umask=0x1,period=100000,event=0xb7,offcore_rsp=0x211umask=0x1,period=100000,event=0xb7,offcore_rsp=0x244offcore_response.corewb.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3808umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F77umask=0x1,period=100000,event=0xb7,offcore_rsp=0x733offcore_response.data_in.remote_cache_dramoffcore_response.demand_data.remote_cache_dramoffcore_response.demand_rfo.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1802umask=0x1,period=100000,event=0xb7,offcore_rsp=0x240SIMD integer 64 bit shuffle/move operationsoffcore_response.any_rfo.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4008umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6033umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4033umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6030umask=0x3,period=2000000,event=0x80rat_stalls.scoreboardumask=0x2,period=2000000,event=0x14br_inst_exec.direct_near_callumask=0x7f,period=20000,event=0x89br_misp_exec.indirect_non_callumask=0x1,period=2000000,cmask=1,event=0xa8lsd_overflowssex_uops_retired.scalar_singleuops_issued.cycles_all_threadsumask=0x4,period=2000000,event=0xc2period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400400004period=100003,umask=0x1,event=0xb0Counts retired load instructions with at least one uop that missed in the L1 cache  Supports address when precise (Precise event)offcore_response.demand_data_rd.l3_hit_e.spl_hitCounts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replaceAll retired load instructions  Supports address when precise (Precise event)offcore_response.other.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC01C0002offcore_response.demand_data_rd.l3_hit_s.snoop_not_neededoffcore_response.demand_rfo.supplier_none.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0100004cmask=1,period=2000003,umask=0x4,event=0x79period=2000003,umask=0x2,event=0xabfrontend_retired.latency_ge_2_bubbles_ge_1frontend_retired.latency_ge_32period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0044000002offcore_response.demand_data_rd.l3_hit_e.snoop_non_dramCounts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)period=2000003,umask=0x4,event=0xc8period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC4000004hle_retired.aborted_memtypeCounts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: SKL091, SKL044Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operationsperiod=100007,umask=0x40,event=0xc4cmask=4,period=2000003,umask=0x4,event=0xa3Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector)period=400009,umask=0x10,event=0xc4Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding loadCounts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel)Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in SkylakeCounts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request typeThis event counts the total number of L2 cache references and the number of L2 cache misses respectivelyThis event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event)This event counts the number of load uops reissued from RehabqCounts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080000008This event counts all instruction fetches, not including most uncacheable
fetchesmem_load_uops_misc_retired.llc_missCounts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10433umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400240Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dramoffcore_response.pf_l_data_rd.llc_miss_local.dramumask=0x2,period=100000,event=0xb0umask=0x1,period=100000,event=0xb7,offcore_rsp=0x80ffREQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = DATA_IN and RESPONSE = ANY_LOCATIONREQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = OTHER and RESPONSE = LOCAL_CACHEumask=0x1,period=100000,event=0xb7,offcore_rsp=0x250REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5020REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3008offcore_response.demand_ifetch.other_local_dramumask=0x1,period=100000,event=0xb4dtlb_misses.large_walk_completedumask=0x20,period=200000,event=0x49umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2720mem_load_l3_miss_retired.local_dramRetired load instructions which data sources missed L3 but serviced from local DRAM  Supports address when precise (Precise event)Retired load instructions whose data sources was remote HITM  Supports address when precise (Precise event)Counts all demand code reads that hit in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010080offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000004offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dramCounts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000020core_power.lvl1_turbo_licenseCounts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly1000 * l2_lines_out.non_silent / inst_retired.anySummary;Power( unc_iio_data_req_of_cpu.mem_read.part0 + unc_iio_data_req_of_cpu.mem_read.part1 + unc_iio_data_req_of_cpu.mem_read.part2 + unc_iio_data_req_of_cpu.mem_read.part3 ) * 4 / 1000000000 / duration_timeinst_retired.any / br_inst_retired.far_branch:uAll DRAM CAS Commands issued. Unit: uncore_imc Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads.  Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request)upi_data_bandwidth_txunc_iio_data_req_of_cpu.mem_read.part0PCI Express bandwidth reading at IIO, part 2. Unit: uncore_iio PCI Express bandwidth reading at IIO, part 3. Unit: uncore_iio fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83,ch_mask=0x1fMulti-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe. Unit: uncore_cha umask=0x10,event=0x50Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHACounts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineClockticks of the IIO Traffic Controller. Unit: uncore_iio Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busWrite request of up to a 64 byte transaction is made to IIO Part0 by the CPU. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_read.part3unc_iio_txn_req_of_cpu.mem_read.part2Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)Multi-socket cacheline Directory update from A to S. Unit: uncore_m2m umask=0x4,event=0x2eumask=0x2,event=0x12unc_upi_rxl_flits.all_dataevent=0x41Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event  Supports address when precise (Precise event)offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080491offcore_response.all_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_pf_rfo.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040120This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020004This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100400offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwdoffcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020020This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020080offcore_response.pf_l3_rfo.l3_hit_e.snoop_missoffcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100100offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoopOCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEOCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C0007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10100007F7ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwdOCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000122ocr.all_rfo.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000122ocr.demand_code_rd.l3_miss.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000002Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC008000ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000400ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000100ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000100This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.other.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwdoffcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_neededOCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_e.snoop_missOCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISSOCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_m.snoop_noneocr.all_pf_rfo.l3_hit_s.snoop_noneOCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.all_rfo.l3_hit.hitm_other_coreOCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_e.hit_other_core_fwdOCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_rfo.supplier_none.hit_other_core_fwdOCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit.hit_other_core_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDEDCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_m.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit.snoop_missocr.demand_data_rd.l3_hit_f.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit_s.hitm_other_coreocr.other.l3_hit_m.any_snoopocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWDCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOPCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_m.any_snoopocr.pf_l3_data_rd.l3_hit_s.no_snoop_neededocr.pf_l3_rfo.l3_hit_m.snoop_missocr.pf_l3_rfo.supplier_none.hitm_other_coreevent=0xe7unc_m_pmm_cmd1.allTag Hit; Read Hit from NearMem, Dirty  LineCounts retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event)Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event)Counts retired load instructions that true miss the STLB  Supports address when precise (Precise event)Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalledcmask=1,inv=1,period=1000003,umask=0x1,event=0x9cperiod=100007,umask=0x1,event=0xc6,frontend=0x500106Counts cycles where a code fetch is stalled due to L1 instruction cache tag missidq.ms_cycles_anyCounts the number of times a TSX Abort was triggered due to commit but Lock Buffer not emptyocr.demand_rfo.l3_missperiod=100003,umask=0x8,event=0xc9Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0010Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sentuops_dispatched.port_1period=50021,umask=0x80,event=0xc5Counts taken conditional mispredicted branch instructions retired (Precise event)Page walks completed due to a demand data load to a 2M/4M pageNumber of page walks outstanding for a demand load in the PMH each cycleCounts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the unmodified data to the requesting coreumask=0x01,event=0x45PMM Read Queue Inserts. Unit: uncore_imc PMM Commands : Reads - RPQ. Unit: uncore_imc umask=0x04,event=0xeaunc_cha_llc_victims.allumask=0xCCC7FE01,event=0x35unc_cha_tor_occupancy.io_hitunc_cha_tor_inserts.ia_miss_drd_prefumask=0xCC43FF04,event=0x35TOR Occupancy : DRds issued by iA Cores. Unit: uncore_cha umask=0xC8168A01,event=0x35unc_cha_tor_inserts.io_miss_pcirdcurunc_iio_txn_req_of_cpu.cmpd.part3unc_iio_data_req_of_cpu.mem_write.part5fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0x83unc_iio_data_req_of_cpu.cmpd.part7unc_iio_num_req_of_cpu.commit.allPCIe Completion Buffer Inserts of completions with data: Part 6. Unit: uncore_iio fc_mask=0x04,umask=0x80,event=0xd5unc_iio_comp_buf_occupancy.cmpd.part6fc_mask=0x04,umask=0x40,event=0xd5unc_iio_comp_buf_occupancy.cmpd.all_partsMulti-socket cacheline Directory Lookups : Found in A state. Unit: uncore_m2m Counts the number of store uops retired. This event is Precise Event capable  Supports address when precise (Precise event)Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0 (Precise event)DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channelunc_cha_tor_inserts.ia_miss_drd_opt_prefClockticks of the mesh to memory (M2M)Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cacheCounts the number of load uops retired that hit in the L3 cache (Precise event)Counts the number of unhalted cycles a core is blocked due to an accepted lock it issuedCounts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be importantCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine cleartopdown_be_bound.allCounts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictionsperiod=1000003,umask=0x1,event=0x71period=1000003,umask=0x10,event=0x71Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counterperiod=200003,umask=0xe,event=0x8period=200003,umask=0x13,event=0xd0event=0x8bDynamic Indirect Predictionsbp_de_redirectThe number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLBIC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another coreAll L2 Cache Requests (Breakdown 1 - Common). Data cache storesAll L2 Cache Requests (Breakdown 2 - Rare). Data cache read sizedAll L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheablel2_request_g2.ic_rd_sized_ncumask=0x80,event=0x64umask=0x01,event=0x6dl3_lookup_state.all_l3_req_typsThe number of retired taken branch instructions that were mispredictedThe number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rareuncore_dfpmcumask=0x38,event=0x187fp_retx87_fp_ops.div_sqr_r_opsfp_retx87_fp_ops.mul_opsMultiply OpsL1 DTLB Miss of a page of 1G sizeTotal Page Table Walks on D-sidels_pref_instr_disp.prefetch_ntaumask=0x04,event=0x4bExecution-Time Branch Misprediction Ratio (Non-Speculative)l1_dtlb_missesThe number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB pageumask=0xff,event=0x85Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an addressls_l1_d_tlb_miss.tlb_reload_coalesced_page_missls_sw_pf_dc_fill.ls_mabresp_rmt_dramde_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stallumask=0x02,event=0xaeumask=0x01,event=0xaeMultiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventLoad Store Allocations. Counts when a LS pipe allocates a MAB entryL1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLBSoftware Prefetch Data Cache Fills by Data Source. From Local L2 to the coreevent=0x5fde_dis_dispatch_token_stalls1.fp_flush_recovery_stalll1_data_cache_fills_from_memoryFR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPAREFR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULLFR_NUMBER_OF_BREAKPOINTS_FOR_DR0L1_DCACHE_WBL2_STORE_MERGEDAXI_READEVENT_24HEVENT_32HEVENT_39HEVENT_78HEVENT_91HEVENT_96HEVENT_D4HEVENT_EBHEVENT_EEHDATA_MAIN_TLB_MISS_STALLEXC_RETURNBR_PREDL2D_CACHETTBR_WRITE_RETIREDL2D_TLB_REFILL_RDL2D_TLB_WRINST_KERNELMISPREDICTED_BRANCH_LIKELY_INSNSNOP_INSNSISPRAM_EVENTSREPLAYCSRCL1_DATA_TOTAL_HITSBUS_RETRY_DUE_TO_COLLISIONCYCLES_SU1_SCHED_STALLEDSTORES_COMPLETEDDATA_MMU_BUSYCRIT_INPUT_INTR_LATENCY_CYCLESDAC2S_DTECTEDk8-ic-misssspiggybackrdszdwordPPC_POWER8DISABLEDALLOCATEDmetric_group: %s
l3_comb_clstr_state.request_misshw_interrupts.receivedGenuineIntelMemory_Bound;Memory_BWUtilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accessesPoweroffcore_requests.demand_rfoThis event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.
Note: Writeback pending FIFO has six entriesThis is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)mem_load_uops_l3_hit_retired.xsnp_missumask=0x1,period=20011,event=0xd2umask=0x4,period=20011,event=0xd2umask=0x20,period=100007,event=0xd3RFO requests that access L2 cacheThis event counts L1D writebacks that access L2 cacheL2 cache lines in I state filling L2umask=0x10,period=100003,event=0xc1umask=0x8,cmask=1,period=2000003,event=0x79This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)umask=0x1,period=2000003,event=0x80Number of times an HLE execution aborted due to incompatible memory typeumask=0x1,period=2000003,event=0xc9Number of times an RTM execution aborted due to HLE-unfriendly instructionsumask=0x80,period=2000003,event=0xc9Loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=2000003,event=0x63inv=1,umask=0x1,cmask=1,period=2000003,event=0xeumask=0x1,period=2000003,event=0x14umask=0x4,period=1000003,event=0x58umask=0x82,period=200003,event=0x88Speculative and retired indirect branches excluding calls and returnsumask=0x1,period=2000003,event=0xa1Cycles per thread when uops are executed in port 1uops_dispatched_port.port_2Cycles per thread when uops are executed in port 2resource_stalls.rscycle_activity.cycles_l2_pendingcycle_activity.stalls_ldm_pendingcycle_activity.cycles_l1d_missumask=0x2,period=2000003,event=0xb1uops_executed.core_cycles_ge_1inst_retired.prec_distActually retired uops. (Precise Event - PEBS)  Supports address when precise (Precise event)Retirement slots used. (Precise Event - PEBS) (Precise event)This event counts both thread-specific (TS) and all-thread (AT) nukesumask=0x3,event=0x35,filter_opc=0x187,filter_nc=1Memory controller clock ticks. Unit: uncore_imc event=0x80,occ_sel=1power_state_occupancy.cores_c6 %(unc_p_freq_max_limit_thermal_cycles / unc_p_clockticks) * 100.dtlb_load_misses.stlb_hit_2mThis event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.stlb_hit_2mpage_walker_loads.itlb_l31 - ( (idq_uops_not_delivered.core / (4 * cycles)) + (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles)) + (uops_retired.retire_slots / (4 * cycles)) )IpTBBranch instructions per taken branch4 * cyclesTLB_SMToffcore_response.demand_code_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020020offcore_response.pf_l3_data_rd.l3_hit.snoop_missoffcore_response.pf_l3_data_rd.l3_hit.any_snoopoffcore_response.pf_l3_rfo.supplier_none.snoop_not_neededoffcore_response.pf_l3_rfo.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020200offcore_response.other.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020240Counts all demand & prefetch data readsoffcore_response.demand_code_rd.l3_miss.snoop_noneoffcore_response.corewb.l3_miss.snoop_noneoffcore_response.corewb.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000020offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_missoffcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000100offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_missoffcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_missoffcore_response.all_pf_data_rd.l3_miss.snoop_not_neededoffcore_response.all_pf_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0240offcore_response.all_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=2000003,cmask=2,event=0xb1umask=0x1,period=2000003,cmask=3,event=0xb1L3 Lookup any request that access cache and found line in E or S-stateumask=0x02,event=0x80Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal caseumask=0x01,event=0x84umask=0x01,event=0Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: BDE70 (Precise event)Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts all requests miss in the L3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00091Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data. Unit: uncore_qpi (unc_m_power_self_refresh / unc_m_clockticks) * 100.l2_lines_out.self.demandl2_ld.self.any.s_stateumask=0x72,period=200000,event=0x29l2_st.self.i_statel2_st.self.mesiAll data requests from the L1 data cachel2_rqsts.self.any.mesiumask=0x44,period=200000,event=0x30x87_comp_ops_exe.fxch.ssimd_uop_type_exec.arithmetic.arsimd_inst_retired.scalar_doubleRetired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsumask=0x1,period=2000000,event=0xcaicache.accessesumask=0x3,period=2000000,event=0xaaMemory references that cross an 8-byte boundarymisalign_mem_ref.ld_bubbleext_snoop.this_agent.anyumask=0x41,period=2000000,event=0x88Retired branch instructions that were mispredicted not-takenRetired branch instructions that were mispredicted takenITLB hitsumask=0x0,period=200003,event=0x30Counts load uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)Counts store uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)umask=0x43,period=200003,event=0xd0Load uops retired that hit L1 data cache (Precise event capable)  Supports address when precise (Must be precise)Load uops retired that missed L2 (Precise event capable)  Supports address when precise (Must be precise)offcore_response.any_data_rd.l2_hitCounts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000100offcore_response.pf_l2_data_rd.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000010offcore_response.demand_rfo.l2_hitCounts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000001Counts demand cacheable data reads of full cache lines that hit the L2 cacheLoads blocked due to store forward restriction (Precise event capable) (Must be precise)umask=0x0,period=200003,event=0xemachine_clears.disambiguationCounts mispredicted branch instructions retired including all branch types (Must be precise)umask=0xeb,period=200003,event=0xc5Counts core cycles the floating point divide unit is busyCounts store uops retired that caused a DTLB miss  Supports address when precise (Must be precise)Memory uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000011000Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.pf_l1_data_rd.any_responseCounts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystemCounts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultOffcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD78, HSD62, HSD61umask=0x6,period=100003,event=0xf2offcore_response.pf_l3_rfo.l3_hit.any_responseoffcore_response.pf_l3_data_rd.l3_hit.any_responseNote that a whole rep string only counts AVX_INST.ALL onceNumber of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision bufferoffcore_response.pf_l2_data_rd.l3_miss.any_responseoffcore_response.demand_code_rd.l3_miss.local_dramIncrements at the frequency of XCLK (100 MHz) when not haltedCycles per core when uops are executed in port 0uops_retired.core_stall_cyclesAn external snoop misses in some processor coreunc_cbo_cache_lookup.extsnp_mUnit: uncore_cbox L3 Lookup external snoop request that access cache and found line in MESI-stateCycles when PMH is busy with page walksoffcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwdoffcore_response.demand_rfo.llc_miss.local_dramoffcore_response.demand_code_rd.llc_miss.local_dramumask=0x1,period=200003,event=0x27mem_load_uops_retired.llc_hitRetired load uops with L2 cache misses as data sources (Precise event)Retired load uops which data sources were HitM responses from shared LLC (Precise event)Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable addressumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010001Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycleumask=0x8,period=2000003,event=0xacNumber of flags-merge uops allocated. Such uops adds delayExecution stalls while L2 cache miss load* is outstandingumask=0x80,period=100003,event=0xc1umask=0x02,event=0x22unc_cbo_xsnp_response.hitmumask=0x40,event=0x22Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLCoffcore_response.all_pf_data_rd.llc_hit.no_snoop_neededCounts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_code_rd.llc_miss.remote_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400001offcore_response.demand_data_rd.llc_miss.remote_hit_forwardCounts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dramevent=0xcCounts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu freq_ge_1200mhz_cycles %freq_ge_4000mhz_cycles %Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacementThis event counts the number of micro-ops retired (Precise event)This event counts the number of the divide operations executeduops_dispatched.threadumask=0x10,period=100003,event=0x3Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cyclesumask=0x4f,period=2000003,event=0x5bCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu umask=0x2,period=200003,event=0x4mem_uops_retired.hitmCounts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeCounts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Bus locks and split lock requests that accounts for any responseCounts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010200Counts UC code reads (valid only for Outstanding response type)  that accounts for any responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400080Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any responseCounts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.partial_writes.l2_hit_this_tile_moffcore_response.demand_code_rd.l2_hit_this_tile_eoffcore_response.partial_writes.l2_hit_this_tile_eoffcore_response.partial_writes.l2_hit_this_tile_soffcore_response.any_rfo.l2_hit_this_tile_soffcore_response.pf_l2_rfo.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400002offcore_response.pf_l1_data_rd.l2_hit_far_tileoffcore_response.any_request.l2_hit_far_tileCounts any Read request  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeCounts all instruction fetches that hit the instruction cacheoffcore_response.any_read.ddr_faroffcore_response.any_rfo.mcdram_nearoffcore_response.pf_l1_data_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080802000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800004Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)offcore_response.partial_reads.mcdramCounts Software Prefetches that accounts for responses from DDR (local and far)uops_retired.scalar_simdumask=0x40,period=200003,event=0xc2This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counterThis event counts every cycle when a data (D) page walk or instruction (I) page walk is in progressumask=0x8,period=2000000,event=0x51umask=0x2,period=2000000,event=0x43L1D hardware prefetch missesAll L1 writebacks to L2L1 writebacks to L2 in S stateumask=0x4,period=100000,event=0xf1l2_lines_out.anyl2_lines_out.prefetch_dirtyL2 requestsl2_write.lock.i_stateumask=0x1,period=2000000,event=0xcbumask=0x10,period=50000,event=0xb,ldlat=0x4Memory instructions retired above 8192 clocks (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x844Offcore requests satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1033Offcore data reads, RFO's and prefetches that HIT in a remote cache Offcore demand data requests satisfied by the LLC and not found in a sibling coreOffcore demand data reads satisfied by any cache or DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1001Offcore demand code reads satisfied by any cache or DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x180Offcore other requests satisfied by the LLC and not found in a sibling coreOffcore prefetch data requests satisfied by any cache or DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF40All offcore prefetch code readsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1040offcore_response.pf_rfo.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x120umask=0x1,period=100000,event=0xb7,offcore_rsp=0x420offcore_response.pf_rfo.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4720Offcore prefetch requests satisfied by the LLC and HIT in a sibling coreumask=0x4,period=200000,event=0x12128 bit SIMD integer shuffle/move operationsSIMD integer 64 bit arithmetic operationsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6022umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF803umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4010Offcore prefetch code reads that missed the LLCoffcore_response.prefetch.local_dramEarly Branch Prediciton Unit clearsbr_inst_exec.indirect_non_callbr_inst_exec.near_callsCycles when thread is not halted (programmable counter)Instructions retired (fixed counter)resource_stalls.rs_fulluops_executed.core_active_cycles_no_port5Total cycles using precise uop retired event (Precise Event)offcore_response.demand_rfo.l3_hit_m.snoop_not_neededperiod=200003,umask=0x38,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040100001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080028000l2_lines_out.silentperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100028000l2_lines_out.non_silentperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080004offcore_response.demand_data_rd.l3_hit_s.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0400001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001C8000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100001Counts the number of cache line split locks sent to the uncoremem_load_l3_hit_retired.xsnp_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100002Retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event)offcore_response.demand_data_rd.l3_hit_e.snoop_noneCycles where a code fetch is stalled due to L1 instruction cache missRetired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x13period=100007,umask=0x1,event=0xc6,frontend=0x15Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event)This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.
Note: Invoking MITE requires two or three cycles delayNumber of times an RTM execution aborted due to uncommon conditionsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000040004cmask=1,period=2000003,umask=0x10,event=0x60Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFC400002period=100003,umask=0x1,event=0x4cThis event counts not taken branch instructions retired  Spec update: SKL091Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS)exe_activity.2_ports_utilFLOPS;FP_Arith;Instruction_Type1 - cpu_clk_thread_unhalted.one_thread_active / ( cpu_clk_thread_unhalted.ref_xclk_any / 2 )Branches;OSThis event counts the number of retire stores that experienced cache line boundary splitsrehabq.sta_fullAll StoresCounts any rfo reads (demand & prefetch) that miss L2umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008008umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000008CALL counts the number of near CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycleumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0120Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400010REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY IFETCH and RESPONSE = ANY_LOCATIONREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHEoffcore_response.demand_data.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f04REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff02REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf822REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWDoffcore_response.pf_ifetch.any_dram_and_remote_fwdREQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAMperiod=100007,umask=0x1,event=0xd3Counts all prefetch data reads that have any response typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0120Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_data_rd.l3_hit.hitm_other_coreCounts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cacheCounts all demand code reads that miss the L3 and the modified data is transferred from remote cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000002Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800400offcore_response.pf_l2_rfo.l3_miss.any_snoopoffcore_response.pf_l2_rfo.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000100period=200003,umask=0x20,event=0x28Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortlyumask=0xF,event=0x4Counts the number of entries in the Read Pending Queue (RPQ) at each cycle.  This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memoryUncore cache clock ticks. Unit: uncore_cha Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) statefc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc0Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part1fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc0fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x83unc_iio_txn_req_by_cpu.mem_write.part2Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_m2m_direct2core_not_taken_dirstateunc_m2m_direct2core_txn_overrideMulti-socket cacheline Directory lookups (cacheline found in A state). Unit: uncore_m2m unc_upi_rxl_bypassed.slot1Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyRetired load instructions whose data sources was forwarded from a remote cache  Supports address when preciseperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0491offcore_response.all_data_rd.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400491This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwdoffcore_response.all_pf_data_rd.l3_hit_m.no_snoop_neededoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400490This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.all_pf_rfo.l3_hit_s.no_snoop_neededoffcore_response.all_pf_rfo.l3_hit_s.snoop_missoffcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_reads.supplier_none.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_f.no_snoop_neededoffcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_noneoffcore_response.demand_data_rd.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100002offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80208000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400208000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800048000offcore_response.other.l3_hit_s.hitm_other_coreoffcore_response.other.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoopoffcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_coreoffcore_response.pf_l2_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_e.any_snoopoffcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l3_data_rd.supplier_none.hitm_other_coreoffcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwdoffcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020100OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss.no_snoop_neededocr.all_data_rd.l3_miss.remote_hit_forwardOCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISSocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoopOCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000491ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_noneOCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000490ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwdocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwdOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededocr.all_pf_rfo.l3_miss_local_dram.snoop_noneOCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10040007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000001ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C008000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010008000ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_noneCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOPocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_miss_local_dram.no_snoop_neededoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITMOCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDOCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDOCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISSOCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONEocr.all_data_rd.pmm_hit_local_pmm.any_snoopocr.all_data_rd.supplier_none.hitm_other_coreocr.all_data_rd.supplier_none.hit_other_core_fwdocr.all_pf_data_rd.l3_hit_e.hitm_other_coreocr.all_pf_data_rd.l3_hit_m.hitm_other_coreOCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISSOCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_COREOCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_s.no_snoop_neededOCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_e.snoop_noneOCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_e.hitm_other_coreOCR.ALL_RFO.L3_HIT_F.SNOOP_NONEocr.all_rfo.l3_hit_m.snoop_noneocr.all_rfo.pmm_hit_local_pmm.snoop_not_neededocr.all_rfo.supplier_none.hit_other_core_no_fwdOCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONEocr.demand_code_rd.l3_hit_s.any_snoopocr.demand_code_rd.supplier_none.hitm_other_coreocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwdocr.demand_rfo.l3_hit_m.hit_other_core_no_fwdocr.other.l3_hit_f.snoop_missocr.other.l3_hit_m.snoop_noneCounts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.other.supplier_none.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOPCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_s.no_snoop_neededCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOPCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwdocr.pf_l2_rfo.l3_hit_m.snoop_missocr.pf_l2_rfo.l3_hit_s.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwdocr.pf_l3_data_rd.l3_hit.snoop_missocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwdocr.pf_l3_data_rd.l3_hit_m.any_snoopocr.pf_l3_data_rd.l3_hit_m.no_snoop_neededocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwdocr.pf_l3_data_rd.supplier_none.snoop_missCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDunc_m_pmm_bandwidth.writeperiod=1000003,umask=0x2,event=0x48Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the coreperiod=200003,umask=0x28,event=0x24period=100003,umask=0x10,event=0xc7Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cacheperiod=100003,umask=0x1,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000010ocr.demand_rfo.l3_hit.snoop_not_neededCounts streaming stores that have any type of responseocr.hwpf_l1d_and_swpf.local_dramCounts demand data reads that have any type of responseCounts streaming stores that hit a cacheline in the L3 where a snoop was sent or notCycles when divide unit is busy executing divide or square root operationsCycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathcmask=10,inv=1,period=1000003,umask=0x2,event=0xc2All branch instructions retired (Precise event)uops_executed.cycles_ge_1Cycles when at least one PMH is busy with a page walk for a demand loadPage walks completed due to a demand data load to a 4K pageCounts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cyclemem_load_l3_hit_retired.xsnp_fwdFor every cycle, increments by the number of outstanding data read requests the core is waiting onDRAM Precharge commands. : Precharge due to page table. Unit: uncore_imc Clockticks of the uncore caching &amp;amp; home agent (CHA). Unit: uncore_cha umask=0xC001FF01,event=0x35TOR Inserts : All requests from iA Cores. Unit: uncore_cha umask=0xC817FD01,event=0x35unc_cha_tor_inserts.ia_miss_crdumask=0xC807FE01,event=0x35TOR Occupancy : All requests from IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_miss_itomumask=0xC897FE01,event=0x35unc_cha_tor_inserts.ia_miss_drd_pmmunc_cha_tor_inserts.ia_miss_drd_local_pmmunc_cha_tor_inserts.ia_miss_drd_ddrTOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha fc_mask=0x07,ch_mask=0x02,umask=0x80,event=0x83fc_mask=0x07,ch_mask=0x01,umask=0x80,event=0x84fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0xc0unc_iio_data_req_of_cpu.cmpd.part4unc_iio_data_req_of_cpu.cmpd.part6unc_iio_txn_req_of_cpu.mem_read.part7unc_i_clockticksValid Flits Sent : All Data. Unit: uncore_upi ll Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts the number of load uops retired that hit in the level 2 cache  Supports address when precise (Precise event)Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  The core frequency may change from time.  This event is not affected by core frequency changes and at a fixed frequency.  This event uses fixed counter 2Counts the number of branch instructions retired for all branch types (Precise event)Counts cycles the floating point divider or integer divider or both are busy.  Does not imply a stall waiting for either dividerTOR Inserts; Data read opt from local IA that misses in the snoop filterperiod=200003,umask=0x1,event=0xd1Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cachebus_lock.lock_cyclesc0_stalls.load_dram_hitThis event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HITperiod=200003,umask=0x4,event=0xcbperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10002period=1000003,umask=0x4,event=0x74Counts the number of Extended Page Directory Pointer Entry hitsCounts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page faultCounts the number of store ops retired that miss in the second level TLB  Supports address when precise (Precise event)umask=0x02,event=0x87event=0xc1The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)ex_ret_brn_ind_mispex_ret_condTotal number of fp uOps on pipe 1umask=0x02,event=0x2This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPSfp_retired_ser_ops.x87_ctrl_retThe number of serializing Ops retired. x87 bottom-executing uOps retiredls_locks.bus_lockumask=0x02,event=0x29Counts the number of loads dispatched to the LS unit. Unit Masks ADDedumask=0x80,event=0x45Total Page Table Walks IC Type 1Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailabled_ratio(ex_ret_brn_misp, ex_ret_brn)L3 Accesses. Unit: uncore_l3pmc All TLBs FlushedThe number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB pageThe number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB pagebp_l1_tlb_miss_l2_tlb_miss.if4kSoftware Prefetch Data Cache Fills by Data Source. Local L2 hitCycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stallCore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. ModifiableL2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 cachesThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced pageic_tag_hit_miss.instruction_cache_hitx87 bottom-executing ops retired. The number of serializing Ops retiredAll Allocations. Counts when a LS pipe allocates a MAB entryls_mab_alloc.load_store_allocationsDemand Data Cache Fills by Data Source. From CCX Cache in different NodeCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination registerumask=0xf0,event=0x64IC_MISSFR_RETIRED_UOPSFR_RETIRED_BRANCHESFR_RETIRED_BRANCHES_MISPREDICTEDFR_RETIRED_TAKEN_BRANCHES_MISPREDICTEDFR_RETIRED_RESYNCSFR_INTERRUPTS_MASKED_CYCLESFR_NUMBER_OF_BREAKPOINTS_FOR_DR2L2_CACHE_REFILLEVENT_05HEVENT_16HEVENT_38HEVENT_69HEVENT_99HEVENT_AAHEVENT_AEHPLE_FIFO_OVERFLOWL2D_CACHE_WB_VICTIMLDREX_SPECVFP_SPECL1D_CACHE_REFILL_OUTERRETURN_NOTPREDDTLB_ACCESSIFU_IDU_MISS_PRED_UPSTREAM_CYCLESLOAD_STORE_REPLAYSEJTAG_INSN_TRIGGERSWBUFBFILLIOBDMALOAD_MISS_ALIASL1_DATA_LOAD_HITBTIC_MISSDTLB_HW_SEARCH_CYCLESFP_STORE_DOUBLE_COMPLETES_IN_LSUBUS_RETRY_DUE_TO_INTERVENTION_ORDERINGGROUP_DISPATCHFXU_LONG_INSTR_COMPLETION_STALLERAT_INSTR_MISSBRANCH_TAKENTLB_DATA_MISSTLB_INSTR_MISSCYCLES_MU_SCHED_STALLEDLOAD_MISS_LDQ_FULLSTORE_TRANSLATE_WHEN_QUEUE_FULLLV2_VSSTASH_REQUESTS_L1DVT5_DETECTEDbranchesSYSTEMPPC7450INTEL_COREI7desc: %s
l3_thread_mask{"type": "sysexit"{"type": "map_in"Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructionsActual Average Latency for L1 data-cache miss demand loadsTLBl2_rqsts.rfo_missl2_rqsts.all_demand_missAll requests that miss L2 cacheDemand Data Read requestsCore-originated cacheable demand requests that refer to L3Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76offcore_requests_outstanding.cycles_with_demand_data_rdCycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76umask=0x82,period=2000003,event=0xd0l2_trans.rfol2_trans.code_rdumask=0x10,period=200003,event=0xf0umask=0x40,period=200003,event=0xf0This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejectsfp_assist.x87_inputumask=0x18,cmask=1,period=2000003,event=0x79hle_retired.aborted_misc4rtm_retired.aborted_misc2umask=0x1,period=20011,event=0xcd,ldlat=0x10umask=0x1,period=2003,event=0xcd,ldlat=0x40event=0x3c,any=1cpu_clk_unhalted.ref_tscld_blocks.store_forwardFalse dependencies in MOB due to partial compareumask=0x3,any=1,cmask=1,period=2000003,event=0xdCycles when divider is busy executing divide operationsrs_events.empty_endNot taken speculative and retired mispredicted macro conditional branchesThis event counts not taken speculative and retired mispredicted macro conditional branch instructionsThis event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0umask=0x8,period=2000003,event=0xa1umask=0x40,period=2000003,event=0xa1umask=0x80,any=1,period=2000003,event=0xa1Cycles stalled due to no store buffers available. (not including draining form sync)uops_executed.core_cycles_ge_2Cycles without actually retired uopsThis event counts cycles without actually retired uopsThis event counts far branch instructions retired  Spec update: BDW98event=0llc_misses.mmio_writellc_misses.pcie_writeunc_h_requests.readsumask=0x40,event=0x21unc_m_power_critical_throttle_cycles(unc_p_power_state_occupancy.cores_c3 / unc_p_clockticks) * 100.(unc_p_prochot_external_cycles / unc_p_clockticks) * 100.unc_p_freq_max_limit_thermal_cyclesDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)  Spec update: BDM69dtlb_store_misses.walk_completed_4kumask=0x12,period=2000003,event=0xbcidq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))BrMispredicts_SMTAverage external Memory Bandwidth Use for reads and writes [GB / sec]64 * ( arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@ ) / 1000000 / duration_time / 1000Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cacheumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0001offcore_response.demand_rfo.l3_hit.any_snoopoffcore_response.corewb.supplier_none.snoop_missoffcore_response.corewb.l3_hit.any_snoopoffcore_response.pf_l3_data_rd.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) RFOs have any response typeoffcore_response.pf_l3_code_rd.supplier_none.snoop_not_neededoffcore_response.all_pf_rfo.l3_hit.snoop_noneoffcore_response.all_rfo.supplier_none.snoop_hit_no_fwdThis is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable  Spec update: BDM30Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)Randomly selected loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000002offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000122umask=0x5,period=2000003,cmask=5,event=0xa3unc_cbo_xsnp_response.miss_evictionumask=0x81,event=0x22umask=0x81,event=0x34L3 Lookup read request that access cache and found line in I-stateumask=0x88,event=0x34umask=0x86,event=0x34Unit: uncore_cbox L3 Lookup write request that access cache and found line in E or S-stateuncore_ncuThis event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)Taken branch instructions retired (Precise event)umask=0x50,period=200000,event=0x26umask=0x71,period=200000,event=0x29l2_ld.self.demand.mesiumask=0x4f,period=200000,event=0x29l2_lock.self.i_statel1d_cache.replModified cache lines allocated in the L1 data cachefp_assist.ssimd_uop_type_exec.unpack.sumask=0x20,period=200000,event=0x9Outstanding cacheable data read bus requests durationumask=0x40,period=200000,event=0x6bumask=0x0,period=200000,event=0x7aumask=0x1,period=2000000,event=0x88umask=0x4,period=2000000,event=0x88Retired mispredicted branch instructions (precise event) (Precise event)umask=0x1,period=200000,event=0xcCounts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchyCounts the number of memory uops retired that is either a loads or a store or both  Supports address when precise (Must be precise)mem_load_uops_retired.wcb_hitCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200002000Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000041000offcore_response.corewb.l2_hitoffcore_response.demand_rfo.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000002umask=0x1,period=200003,event=0xe7Store uops that split a page (Precise event capable) (Must be precise)Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the dataumask=0x0,period=200003,event=0x86Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise)Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise)umask=0xfe,period=200003,event=0xc5umask=0x0,period=2000003,event=0xcdCycles a divider is busyCycles the integer divide unit is busyCounts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBCounts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cacheoffcore_response.any_data_rd.any_responseCounts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Page walk completed due to a demand data store to a 4K pagePage walk completed due to a demand data store to a 1GB pageoffcore_response.all_data_rd.l3_hit.hitm_other_coreNumber of transitions from legacy SSE to AVX-256 when penalty applicable  Spec update: HSD56, HSM57 (Precise event)output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise event)umask=0x1,period=100003,event=0xcd,ldlat=0x20miss the L3 and the data is returned from local dramCounts all prefetch (that bring data to LLC only) code reads miss in the L3False dependencies in MOB due to partial compare on addressAliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impactFP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling (Precise event)Unit: uncore_cbox L3 Lookup write request that access cache and found line in I-stateL3 Lookup external snoop request that access cache and found line in E or S-stateStore misses in all DTLB levels that cause page walksITLB misses that hit STLB (2M)Number of DTLB page walker loads from memory  Spec update: HSD25page_walker_loads.ept_dtlb_l2umask=0x82,period=2000003,event=0xbcRetired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event)umask=0x20,period=100003,event=0xd3Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: HSD56, HSM57Retired load uops that split across a cacheline boundary. (Precise Event)l2_lines_out.dirty_allumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0244umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0091Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x20,period=2000003,event=0x10Cycles per thread when uops are dispatched to port 0A snoop invalidates a non-modified line in some processor coreUnit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c03f7offcore_response.other.portio_mmio_ucoffcore_response.pf_llc_data_rd.llc_hit.snoop_missumask=0x1,event=0x35,filter_opc=0x1e4unc_q_txl_flits_g0.non_dataNot rejected writebacks from L1D to L2 cache lines in S stateumask=0x1,period=100003,event=0xb7,offcore_rsp=0x187FC20077umask=0x1,period=2000003,event=0x17umask=0x40,period=2000003,event=0xdumask=0x2,period=100007,event=0xc5This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issuedinv=1,umask=0x1,edge=1,period=2000003,cmask=1,event=0x5eCounts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts Software Prefetches that accounts for any responseCounts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts L2 code HW prefetches that accounts for any responseoffcore_response.demand_code_rd.l2_hit_near_tile_mCounts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002002000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008003091offcore_response.demand_code_rd.l2_hit_near_tileCounts any Prefetch requests that accounts for data responses from DRAM LocalCounts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit farCounts Demand cacheable data write requests  that accounts for data responses from DRAM FarCounts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101003091offcore_response.any_request.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100401000offcore_response.demand_rfo.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400002Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600044offcore_response.any_data_rd.ddrCounts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front endCounts the number of occurences a retired store that is a cache line split. Each split should be counted only onceumask=0x40,period=200003,event=0x3Counts the number of mispredicted near relative CALL branch instructions retired (Precise event)Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be includedL1 data cache load lock hitsL2 data prefetches in E stateumask=0xaa,period=200000,event=0x24l2_transactions.l1d_wbAll demand L2 lock RFOs that hit the cacheumask=0xf0,period=100000,event=0x27umask=0xe,period=100000,event=0x27Offcore data reads satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F44offcore_response.any_ifetch.any_locationoffcore_response.any_ifetch.io_csr_mmioOffcore code reads that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FFOffcore RFO requests satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F08offcore_response.corewb.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8077umask=0x1,period=100000,event=0xb7,offcore_rsp=0x477umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F33umask=0x1,period=100000,event=0xb7,offcore_rsp=0x433offcore_response.demand_data_rd.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8001Offcore demand data reads satisfied by the LLCOffcore demand data reads that HITM in a remote cacheoffcore_response.demand_ifetch.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1004All offcore demand RFO requestsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x802offcore_response.other.any_locationoffcore_response.other.remote_cacheOffcore prefetch code reads satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8020Offcore prefetch requests that HIT in a remote cacheSSE2 integer Uopsfp_mmx_trans.any128 bit SIMD integer multiply operationssimd_int_64.packed_arithMacro-fused instructions decodedOffcore data reads satisfied by the local DRAMoffcore_response.any_request.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2022umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2003umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF830umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF840umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4070Offcore prefetch requests satisfied by a remote DRAMSegment rename stall cyclesbr_inst_exec.return_nearumask=0x4,period=200000,event=0xc4inv=1,umask=0x1,period=2000000,cmask=16,event=0xc0Resource related stall cyclesuop_unfusionuops_executed.port4_coreFused Uops issuedumask=0x1,period=200000,event=0x49offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwdCounts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncoreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801C0002offcore_response.other.l3_hit_m.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020001offcore_response.demand_data_rd.l3_hit_e.snoop_hitml2_lines_out.useless_hwpfperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001C0002offcore_response.demand_code_rd.l3_hit_e.snoop_noneoffcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwdperiod=100003,umask=0x2,event=0xd1offcore_response.demand_rfo.l3_hit_s.snoop_missoffcore_response.demand_code_rd.l3_hit_m.snoop_noneAny memory transaction that reached the SQoffcore_response.demand_data_rd.l4_hit_local_l4.spl_hitoffcore_response.other.l3_hit_s.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100004offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080001Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularitycmask=1,period=2000003,umask=0x24,event=0x79icache_64b.iftag_hitInstruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularityperiod=2000003,umask=0x1,event=0x9crtm_retired.aborted_memtypeoffcore_response.demand_data_rd.l3_hit_s.snoop_non_dramoffcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dramperiod=2000003,umask=0x8,event=0xc8Counts the number of machine clears due to memory order conflicts  Spec update: SKL089period=2000003,umask=0x10,event=0x54period=2000003,umask=0x80,event=0xa1period=2000003,umask=0x4,event=0xc2IpFarBranchcmask=1,period=100003,umask=0x10,event=0x49Store address buffer fullrehabq.any_stCountsof demand RFO requests to write to partial cache lines that miss L2Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related informationThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclearsI-side page-walksRetired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event)All retired store uops. (Precise Event - PEBS) (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0244offcore_response.all_pf_rfo.llc_hit.any_responseoffcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwdoffcore_response.pf_l2_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400200Offcore demand data read requestsumask=0x2,period=2000000,cmask=1,event=0x60umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff11offcore_response.data_ifetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5077umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5033offcore_response.demand_data_rd.local_dram_and_remote_cache_hitREQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f02REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff50REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIToffcore_response.prefetch.local_dram_and_remote_cache_hitoffcore_response.any_data.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf844offcore_response.any_request.any_dram_and_remote_fwdREQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_DATA and RESPONSE = ANY_LLC_MISSExtended Page Table walk cyclesumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2710offcore_response.all_pf_rfo.l3_hit.no_snoop_neededoffcore_response.all_rfo.l3_hit.snoop_hit_with_fwdoffcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwdCounts all demand data writes (RFOs) that hit in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0400OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l2_rfo.l3_hit.no_snoop_neededNumber of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per elementCounts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dramCounts demand data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwdoffcore_response.pf_l3_data_rd.l3_miss.any_snoopCounts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cacheCore cycles the out-of-order engine was throttled due to a pending power level requestCounts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-ModeCounts the number of writes requests allocated into the Write Pending Queue (WPQ).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller).  The write requests deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMCunc_cha_requests.readsCounts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was neededumask=0x02,event=0xa5umask=0x08,event=0x39unc_cha_sf_eviction.m_stateumask=0x01,event=0x5cfc_mask=0x4,ch_mask=0x01,umask=0x03,event=0xc2fc_mask=0x4,ch_mask=0x04,umask=0x03,event=0xc2unc_iio_data_req_by_cpu.mem_read.part3Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busCounts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc0fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc1unc_iio_txn_req_by_cpu.mem_write.part1unc_iio_txn_req_by_cpu.peer_read.part0fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x84fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x84RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline. Unit: uncore_irp event=0x23umask=0x2,event=0x2dMulti-socket cacheline Directory update from/to Any state. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable MemoryAD Ingress (from CMS) Occupancyunc_upi_rxl_bypassed.slot0offcore_response.all_data_rd.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.all_pf_rfo.l3_hit.hit_other_core_fwdoffcore_response.all_reads.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001007F7This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.all_rfo.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.demand_rfo.supplier_none.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80028000offcore_response.other.supplier_none.hit_other_core_fwdoffcore_response.other.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.supplier_none.snoop_missoffcore_response.pf_l1d_and_sw.supplier_none.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080080offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISSOCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOPocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_missocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC007F7ocr.all_rfo.l3_miss.hit_other_core_fwdOCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONECounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_COREocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000002ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoopCounts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDCounts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwdocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000100This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREOCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOPOCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_m.snoop_noneocr.all_data_rd.supplier_none.snoop_missOCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDOCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONEocr.all_reads.l3_hit.snoop_noneOCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWDOCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_F.HITM_OTHER_COREocr.all_reads.l3_hit_m.hit_other_core_no_fwdocr.all_rfo.l3_hit.hit_other_core_no_fwdOCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISSocr.all_rfo.l3_hit_e.hit_other_core_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.demand_data_rd.supplier_none.hit_other_core_no_fwdCounts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWDCounts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWDocr.other.l3_hit_f.hitm_other_coreCounts any other requests  OCR.OTHER.L3_HIT_M.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_e.snoop_noneocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_f.any_snoopocr.pf_l3_data_rd.l3_hit_s.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_COREUNC_M_PMM_BANDWIDTH.TOTALWrite Pending Queue Occupancy of all write requests for Intel Optane DC persistent memoryRead requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m Counts demand requests that miss L2 cacheperiod=100003,umask=0x4,event=0xf4Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesSW prefetch requests that hit L2 cacheCounts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructionsperiod=100007,umask=0x1,event=0xc6,frontend=0x504006period=100003,umask=0x2,event=0x5dperiod=100003,umask=0x4,event=0x54Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or notCounts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assistsCore cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructionsocr.demand_rfo.l3_hit.snoop_sentbr_misp_retired.cond_ntakenperiod=50021,umask=0x10,event=0xc5Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stalluops_executed.cycles_ge_4Cycles when RAT does not issue Uops to RS for the threadPage walks completed due to a demand data store to a 2M/4M pageumask=0x04,event=0xd32LM Tag Check : Write Hit in Near Memory Cache. Unit: uncore_imc umask=0x08,event=0x2Remote write requests sent to the CHA's home agent. Unit: uncore_cha umask=0xC80FFE01,event=0x36umask=0xC001FD04,event=0x36umask=0xCC43FE04,event=0x35unc_cha_tor_occupancy.ia_rfoumask=0xC8177E01,event=0x36unc_cha_tor_inserts.ia_miss_drd_remoteunc_cha_tor_inserts.ia_miss_rfo_pref_localumask=0xC8178601,event=0x35unc_iio_data_req_of_cpu.cmpd.part1fc_mask=0x07,ch_mask=0x08,umask=0x80,event=0x83unc_iio_data_req_by_cpu.mem_write.part6fc_mask=0x07,ch_mask=0xFF,umask=0x01,event=0x85unc_iio_txn_req_of_cpu.cmpd.part6fc_mask=0x04,ch_mask=0x01,umask=0x03,event=0xc2PCIe Completion Buffer Occupancy of completions with data : Part 3. Unit: uncore_iio M2M Writes Issued to iMC : PMM - All Channels. Unit: uncore_m2m Clockticks of the mesh to UPI (M3UPI). Unit: uncore_m3upi Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)unc_cha_tor_inserts.ia_miss_wcilfData requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1period=200003,umask=0x4f,event=0x2eCounts the number of cycles the core is stalled due to a demand load which hit in the L2 cacheperiod=1000003,umask=0x20,event=0x71Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache missescycles / cpu_clk_unhalted.ref_tscCounts the number of BACLEARS due to a return branchbus_lock.self_lockstopdown_bad_speculation.allCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clearCounts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorizedperiod=200003,umask=0xfb,event=0xc4period=200003,umask=0x10,event=0x8Counts the number of Extended Page Directory Entry hitsumask=0x08,event=0x60l2_request_g1.group2umask=0x01,event=0x62l2_cache_req_stat.ic_fill_missRetired InstructionsRetired UopsThe number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interruptsumask=0x01,event=0xcbevent=0xd3umask=0x02,event=0x1cfex_ret_fus_brnch_instdram_channel_data_controller_5Total number multi-pipe uOps assigned to all pipesThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Opsls_mab_alloc.storesLS MAB allocates by type - loadsls_l1_d_tlb_miss.tlb_reload_32k_l2_hitl3_accessesL3 Misses (includes Chg2X). Unit: uncore_l3pmc ic_fetch_miss_ratioNumber of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesumask=0x01,event=0xeL1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLBde_dis_uops_from_decoder.opcache_dispatchedCount of dispatched Ops from OpCached_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss)Instruction Cache Hit. Counts various IC tag related hit and miss eventsL2 Cache Misses from L2 Cache HWPFDC_ACCESSDC_MISSIC_L1_ITLB_MISS_AND_L2_ITLB_HITNB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDNB_MEMORY_CONTROLLER_TURNAROUNDCLOCK_CYCLESL2_ACCESSL2_CACHE_NEON_MEM_ACCESSPRED_BRANCH_EXEC_TAKENEVENT_01HEVENT_13HEVENT_27HEVENT_2DHEVENT_44HEVENT_70HEVENT_72HEVENT_75HEVENT_7EHEVENT_80HEVENT_8DHEVENT_9AHEVENT_AFHEVENT_B4HEVENT_C2HEVENT_CFHEVENT_E0HEVENT_FAHEVENT_FFHINTEGER_CORE_CLOCK_ENABLEDDSB_SPECLL_CACHE_MISS_RDINTEGER_COMPLETEDLDQ_LT_QUARTERICACHE_MISS_STALLSALU_BUBBLE_CYCLESDCACHE_WRITEBACKSL2_CACHE_WRITEBACKSWBB_FULL_STALLSDSP_INSNSDMLDSVIU2_INSTR_COMPLETEDTLBIE_INSTR_COMPLETEDVR_ISSUE_QUEUE_DISPATCHESTHRESHOLD_TIMEOUTSTOP_COMPLETIONERAT_DATA_MISSINSTR_L1_CACHE_FETCHESEXT_INPUT_INTR_PENDING_LATENCY_CYCLESSTASH_HITSDVT6_DETECTEDP6BRANCH-INSTRUCTION-RETIREDBRANCH-MISSES-RETIREDLLC_MISS_RHITMRESOURCE_STALLS.ANYHygonGenuine{"type": "pmcallocatedyn"GenuineIntel-6-57bdwde metricsPipeline;Ports_UtilizationCPU_Utilization( 1*( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2* fp_arith_inst_retired.128b_packed_double + 4*( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8* fp_arith_inst_retired.256b_packed_single ) / 1000000000 / duration_timel2_rqsts.all_code_rdumask=0x50,period=200003,event=0x27mem_load_uops_l3_hit_retired.xsnp_hitumask=0x10,period=100007,event=0xd3Retired load uop whose Data Source was: Remote cache HITM (Precise Event)  Supports address when precise.  Spec update: BDE70l2_trans.demand_data_rdTransactions accessing L2 pipeumask=0x1,period=100003,event=0xf1This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejectsNumber of X87 assists due to output valueCycles Decode Stream Buffer (DSB) is delivering 4 Uopsidq.ms_switchesicache.ifdata_stallmisalign_mem_ref.storestx_mem.abort_conflictumask=0x4,period=2000003,event=0x54Number of times a TSX Abort was triggered due to a non-release/commit store to lockCounts the number of times a XBEGIN instruction was executed inside an HLE transactional regionhle_retired.commitNumber of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)Number of times we entered an RTM region; does not count nested transactionsNumber of times we entered an RTM region
 does not count nested transactionsThis event counts loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)Core cycles when at least one thread on the physical core is not in halt stateReference cycles when the thread is unhalted (counts at 100 MHz rate)umask=0x1,any=1,period=2000003,event=0x3cTaken speculative and retired macro-conditional branch instructions excluding calls and indirectsbr_misp_exec.taken_indirect_near_calluops_executed_port.port_0_coreuops_executed_port.port_1_coreuops_executed_port.port_6_coreThis event counts resource-related stall cycles. Reasons for stalls can be as follows:
 - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)
 - *any* u-arch structure got empty (like INT/SIMD FreeLists)
 - FPU control word (FPCW), MXCSR
and others. This counts cycles that the pipeline backend blocked uop delivery from the front endThis event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front endumask=0x2,cmask=2,period=2000003,event=0xa3uops_retired.total_cyclesbr_inst_retired.not_takenuncore_cboxLLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rsp_fwd_wbuncore_imc(unc_m_power_channel_ppd / unc_m_dclockticks) * 100.event=0x43event=0x80,occ_sel=2(unc_p_power_state_occupancy.cores_c6 / unc_p_clockticks) * 100.umask=0x4,period=100003,event=0x85Number of ITLB page walker hits in the L1+FB  Spec update: BDM69, BDM98TopdownL1Bad_Speculation_SMTInstruction per taken branch( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / cyclesThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Spec update: BDM100.  Supports address when precise (Precise event)Counts all demand code reads have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020004offcore_response.corewb.supplier_none.snoop_hit_no_fwdoffcore_response.corewb.l3_hit.snoop_noneoffcore_response.pf_l2_code_rd.supplier_none.snoop_noneoffcore_response.pf_l2_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0200offcore_response.all_pf_data_rd.l3_hit.snoop_not_neededoffcore_response.all_pf_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010240offcore_response.all_pf_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0091offcore_response.all_rfo.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0122Randomly selected loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_data_rd.l3_miss_local_dram.any_snoopoffcore_response.demand_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000020offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitmoffcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoopoffcore_response.all_pf_data_rd.l3_miss.snoop_noneoffcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000122inv=1,umask=0x1,period=2000003,cmask=1,event=0xeumask=0x8,period=2000003,cmask=8,event=0xa3FP operations  retired. X87 FP operations that have no exceptions: (Precise event)Number of cycles using always true condition (uops_ret < 16) applied to  PEBS uops retired event (Precise event)This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retiredumask=0x01,event=0x81This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)Number of times RTM abort was triggered (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000122l2_ld.self.any.e_stateumask=0x48,period=200000,event=0x29umask=0x44,period=200000,event=0x2eumask=0x52,period=200000,event=0x2el1d_cache.stRetired loads that hit the L2 cache (precise event)simd_uop_type_exec.shift.ssimd_uop_type_exec.pack.arsimd_inst_retired.vectorcycles_icache_mem_stalled.icache_mem_stalledbus_trans_mem.all_agentsAll bus transactionsumask=0x40,period=200000,event=0x7eDivide operations executedumask=0x81,period=2000000,event=0x13resource_stalls.div_busyNumber of I-Side page walksRequests rejected by the XQdl1.dirty_evictionoffcore_response.any_read.l2_miss.anyCounts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem that hit the L2 cacheoffcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000002000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010400Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000004offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x2,period=2000003,event=0umask=0xfd,period=200003,event=0xc4br_inst_retired.taken_jccRetired mispredicted branch instructions (Precise event capable) (Must be precise)umask=0x8,period=200003,event=0xe6Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progressCounts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040400offcore_response.bus_locks.l2_miss.hitm_other_coreCounts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000008000Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystemRetired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise)Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.  The page walks can end with or without a page faultumask=0x8,period=2000003,event=0x49Demand Data Read miss L2, no rejects  Spec update: HSD78Demand Data Read requests that hit L2 cache  Spec update: HSD78Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61Retired load uops with L2 cache misses as data sources  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)offcore_response.all_reads.l3_hit.hitm_other_coreoffcore_response.all_rfo.l3_hit.hit_other_core_no_fwdSSE* FP micro-code assist when output value is invalid (Precise event)Counts cycles DSB is delivered at least one uops. Set Cmask = 1Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135Counts all prefetch (that bring data to LLC only) data reads miss in the L3Counts all prefetch (that bring data to L2) RFOs miss in the L3Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dramoffcore_response.demand_data_rd.l3_miss.local_dramoffcore_response.demand_data_rd.l3_miss.any_responseCounts demand data reads miss in the L3Cycles per core when uops are executed in port 1Cycles allocation is stalled due to resource related reason  Spec update: HSD135Number of instructions at retirement  Spec update: HSD11, HSD140umask=0x28,event=0x22DTLB store misses with low part of linear-to-physical address translation missedCounts the number of Extended Page Table walks from the ITLB that hit in the L1 and FBRetired load uops with L3 cache hits as data sources  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)offcore_response.demand_code_rd.llc_miss.any_responseumask=0x8,period=200003,event=0x28umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0122dsb2mite_switches.count(( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))Number of any page walk that had a miss in LLCLoads with latency value being above 4 (Must be precise)Cycles per thread when load or STA uops are dispatched to port 2Cycles which a Uop is dispatched on port 5Unit: uncore_arb Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCPage walk for a large page completed for Demand loadumask=0x3,period=100007,event=0xd3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0200offcore_response.demand_data_rd.llc_miss.any_dramPCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss. Unit: uncore_cbox LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.miss_opcode.pcie_write. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x1e5unc_p_freq_band1_transitionsCycles spent changing Frequency. Unit: uncore_pcu Retired store uops that split across a cacheline boundary (Precise event)This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Taken speculative and retired mispredicted direct near callsresource_stalls.lbActually retired uops (Precise event)Performance sensitive flags-merging uops added by Sandy Bridge u-archMemory controller clock ticks. Used to get percentages of memory controller cycles events. Unit: uncore_imc Counts all the load micro-ops retiredoffcore_response.any_pf_l2.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080070umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000083091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080400Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l2_code_rd.l2_hit_far_tile_moffcore_response.pf_l2_rfo.l2_hit_near_tile_e_fCounts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts any request that accounts for responses which hit its own tile's L2 with data in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000001offcore_response.demand_code_rd.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000004offcore_response.any_code_rd.l2_hit_this_tile_fCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeCounts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_read.l2_hit_far_tileoffcore_response.any_code_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400080offcore_response.demand_code_rd.ddr_farCounts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)offcore_response.pf_l2_code_rd.ddrCounts any Read request  that accounts for responses from DDR (local and far)umask=0x1,period=200003,event=0xcbFixed Counter: Counts the number of unhalted core clock cyclesCounts the number of mispredicted far branch instructions retired (Precise event)umask=0x01,event=0x2Counts the total I-side page walks that are completedl1d_wb_l2.i_statel2_data_rqsts.anyl2_data_rqsts.prefetch.i_statel2_lines_in.s_stateL2 RFO transactionsInstructions retired which contains a store (Precise Event)Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)Retired loads that hit the L2 cache (Precise Event)umask=0x4,period=40000,event=0xcbumask=0x80,period=4000,event=0xfumask=0x10,period=1000,event=0xb,ldlat=0x80umask=0x10,period=5000,event=0xb,ldlat=0x20umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4711Offcore code reads satisfied by any cache or DRAMOffcore code reads satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3822offcore_response.any_rfo.remote_cache_hitOffcore code or data read requests satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1877offcore_response.demand_data_rd.any_locationAll offcore demand code readsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8004umask=0x1,period=100000,event=0xb7,offcore_rsp=0x204Offcore demand code reads satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F02umask=0x1,period=100000,event=0xb7,offcore_rsp=0x402umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F30umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF30umask=0x1,period=100000,event=0xb7,offcore_rsp=0x210Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unitfp_comp_ops_exe.sse_fp_packedumask=0x40,period=200000,event=0xfdumask=0x1,period=2000000,event=0x19Two Uop instructions decodedumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4022Offcore writebacks to the local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2010offcore_response.pf_rfo.local_draml1i.missesload_dispatch.rs_delayedThread responded HITE to snoopThread responded HITM to snoopumask=0x2,period=2000000,event=0xe6umask=0x7f,period=200000,event=0x88umask=0x20,period=20000,event=0x88br_inst_exec.non_callsRetired floating-point operations (Precise Event)Cycles machine clear asserteditlb_flushoffcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0408000period=100007,umask=0x20,event=0xd1period=200003,umask=0x1,event=0xf2offcore_response.other.supplier_none.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400001offcore_response.demand_code_rd.l3_hit_m.any_snoopThis event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPFoffcore_response.other.l3_hit_e.snoop_not_neededcmask=1,period=2000003,umask=0x4,event=0x60period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080001Retired Instructions who experienced iTLB true miss (Precise event)period=100003,umask=0x1,event=0xe6Retired Instructions who experienced Instruction L2 Cache true miss (Precise event)frontend_retired.latency_ge_512period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000400004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC400004period=2000003,umask=0x80,event=0xc8Number of times an HLE execution aborted due to unfriendly events (such as interrupts)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x20001C8000Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not emptyCycles where the pipeline is stalled due to serializing operationsperiod=100003,umask=0x3f,event=0xc1Counts self-modifying code (SMC) detected, which causes a machine clearcmask=5,period=2000003,umask=0x5,event=0xa3Counts the retirement slots usedCycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in SkylakeCounts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completedCounts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultLoads blocked due to store forward restriction (Precise event)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680003091offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwdCounts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cacheThis event counts the number of load ops retired that had DTLB miss (Precise event)This event counts retired demand loads that missed the  last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event)offcore_response.all_pf_code_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0240offcore_response.demand_rfo.llc_hit.snoop_missCounts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0040Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_code_rd.llc_miss.dramoffcore_response.pf_ifetch.llc_miss_local.dramoffcore_requests_outstanding.demand.rfo_not_emptyumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5003umask=0x1,period=100000,event=0xb7,offcore_rsp=0x850offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hitREQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIOREQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHEumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff20REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITMREQUEST = ANY RFO and RESPONSE = ANY_LLC_MISSoffcore_response.demand_data_rd.any_dram_and_remote_fwdoffcore_response.demand_rfo.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf840DTLB miss page walk cyclesumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2740Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded eventperiod=100007,umask=0x4,event=0xd3Counts prefetch (that bring data to L2) data reads that have any response typeoffcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000100Write Pending Queue Occupancy. Unit: uncore_imc umask=0x21,event=0x35,config1=0x40e33Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and acrossPCIe Completion Buffer occupancy of completions with data: Part 3Read request for up to a 64 byte transaction is made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busevent=0x9unc_upi_clockticksunc_upi_rxl_flits.non_dataumask=0x27,event=0x2Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0491offcore_response.all_data_rd.l3_hit_f.snoop_missoffcore_response.all_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwdoffcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwdoffcore_response.all_pf_data_rd.l3_hit_f.hitm_other_coreoffcore_response.all_pf_data_rd.l3_hit_s.hitm_other_coreoffcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.all_pf_rfo.supplier_none.no_snoop_neededoffcore_response.all_reads.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F802007F7offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020122offcore_response.demand_code_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200001offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONEoffcore_response.demand_rfo.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80088000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800208000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080400offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040080offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONEOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000490ocr.all_pf_rfo.l3_miss.hitm_other_coreocr.all_pf_rfo.l3_miss.hit_other_core_no_fwdocr.all_pf_rfo.l3_miss.remote_hit_forwardocr.all_pf_rfo.l3_miss.snoop_missocr.all_pf_rfo.l3_miss.snoop_noneOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_reads.l3_miss.any_snoopOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_rfo.l3_miss_local_dram.snoop_missCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWDCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000001ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC008000Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410008000ocr.other.l3_miss_remote_hop1_dram.snoop_missCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITMperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONECounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITMCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000020ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000020Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss.snoop_missCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss_local_dram.snoop_missoffcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwdoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_noneoffcore_response.demand_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.other.l3_miss.remote_hitmThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEOCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOPocr.all_data_rd.l3_hit_e.snoop_noneOCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.all_data_rd.supplier_none.any_snoopocr.all_pf_data_rd.l3_hit.no_snoop_neededocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwdocr.all_pf_data_rd.supplier_none.snoop_missocr.all_pf_rfo.l3_hit_s.hitm_other_coreocr.all_pf_rfo.supplier_none.any_snoopocr.all_pf_rfo.supplier_none.hit_other_core_no_fwdocr.all_reads.l3_hit.snoop_missOCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_E.HITM_OTHER_COREOCR.ALL_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_F.ANY_SNOOPOCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDEDCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_e.no_snoop_neededocr.demand_data_rd.l3_hit_s.snoop_missocr.demand_rfo.l3_hit.hit_other_core_no_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_COREocr.other.l3_hit_e.no_snoop_neededocr.other.l3_hit_f.hit_other_core_fwdocr.other.l3_hit_f.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_f.any_snoopCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit.snoop_missocr.pf_l2_rfo.l3_hit_e.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit.hit_other_core_fwdunc_m_pmm_rpq_occupancy.all / unc_m_pmm_rpq_inserts / unc_m_clockticksumask=0x21,event=0x35,config1=0x40433Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailabilityNon-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fillCounts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00020period=100003,umask=0x40,event=0x54period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000020ocr.hwpf_l2_data_rd.local_dramload_hit_prefetch.swpfperiod=100003,umask=0x20,event=0xccNumber of retired PAUSE instructions. This event is not supported on first SKL and KBL productsCounts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired eventCounts Core crystal clock cycles when current thread is unhalted and the other thread is haltedbr_misp_retired.condbr_inst_retired.condCounts the retirement slots used each cycleCycles optimal number of Uops delivered by the LSD, but did not come from the decoderuops_executed.cycles_ge_2C1 residency percent per coreunc_m_wpq_inserts.pch1unc_m_wpq_occupancy_pch0umask=0x08,event=0x50umask=0xC001FE01,event=0x36TOR Inserts : ItoMs issued by IO Devices that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_itomunc_cha_tor_inserts.ia_miss_drd_remote_ddrunc_cha_tor_occupancy.ia_miss_drd_ddrumask=0xC8F3FF04,event=0x35unc_iio_data_req_by_cpu.mem_write.part4fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0xc0fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0xc0fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0xc1unc_iio_txn_req_of_cpu.mem_write.part4fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0x84unc_iio_txn_req_of_cpu.cmpd.part4unc_iio_clockticks_freerunfc_mask=0x04,ch_mask=0x10,umask=0x03,event=0xc2Total IRP occupancy of inbound read and write requests to coherent memory. Unit: uncore_irp FAF RF full. Unit: uncore_irp umask=0x08,event=0x2dunc_u_clockticksCounts the number of instructions retired. (Fixed event) (Precise event)period=20003,event=0xc3umask=0xC001FE01,event=0x35,config1=0x40040e33TOR Inserts; CRd misses from local IA. Unit: uncore_cha Counts the number of load uops retired that hit in the L1 data cache  Supports address when precise (Precise event)Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branchesCounts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguationsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2104000001This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISSThis event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLESperiod=200003,umask=0xbf,event=0xc4Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event)Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1Counts the number of page walks outstanding in the page miss handler (PMH) for loads every cycleperiod=2000003,umask=0x80,event=0x49umask=0x02,event=0x61l2_wcb_req.wcb_closel2_cache_req_stat.ic_fill_hit_xThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructionsRemote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2dram_channel_data_controller_4fpu_pipe_assignment.total2Double precision add/subtract FLOPSfp_ret_sse_avx_ops.sp_div_flopsfp_ret_sse_avx_ops.sp_mult_flopsfp_num_mov_elim_scal_op.sse_mov_opsumask=0x04,event=0x29ls_dispatch.store_dispatchde_dis_dispatch_token_stalls0.alu_token_stallMixed SSE/AVX StallsTotal number uOps assigned to pipe 3fp_disp_faults.x87_fill_faultStore-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element storesNumber of accesses to the dcache for load/store referencesls_l1_d_tlb_miss.tlb_reload_coalesced_page_hitSoftware Prefetch Instructions Dispatched (Speculative)ls_pref_instr_disp.prefetch_wls_hw_pf_dc_fill.ls_mabresp_lcl_cacheDecode Redirectsbp_l1_tlb_miss_l2_tlb_hitumask=0x18,event=0x18eThe number of 64B misaligned (i.e., cacheline crossing) loadsSoftware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same nodeLS_MICROARCHITECTURAL_RESYNC_BY_SNOOPLS_RETIRED_CFLUSH_INSTRUCTIONSIC_INSTRUCTION_FETCH_STALLEVENT_0BHEVENT_12HEVENT_17HEVENT_2AHEVENT_7FHEVENT_82HEVENT_B5HEVENT_DEHEVENT_E3HEVENT_E8HEXTERNAL_INTERRUPTPLE_REQUEST_PROGRAMMEDSTREX_FAIL_SPECEXC_HVCSTALL_BACKENDINST_USERL2_DMISS_STALL_CYCLESFSB_QUARTER_TO_HALFAGCB_FULL_DR_STALLSL2_CACHE_MISS_CYCLESSYSTEM_EVENT_1SYSTEM_EVENT_5SYNCWVIU2_INSTR_WAIT_CYCLESVTQ_LINE_FETCH_HITCYCLES_TWO_INSTR_COMPLETEDL1_DATA_CACHE_CASTOUTS_TO_L2CYCLES_RUNNINGL1_LOAD_MISSPMC1_OVERFLOWPMC3_OVERFLOWDLFB_RETRIES_TO_MBARL2_CACHE_DIRTY_UPDATESstore-pipe-junk-opsexclusivesse-and-x87-microtrapsEDGEPOWER8INTEL_P5ARMV8_CORTEX_A57TSSTOPPEDtrueGenuineIntel-6-36v19GenuineIntel-6-A7Pipeline;SummarycacheRFO requests that miss L2 cachel2_rqsts.all_demand_referencesThis event counts duration of L1D miss outstanding in cyclesumask=0x2,cmask=1,period=2000003,event=0x48umask=0x4,period=2000003,event=0x60This event counts both cacheable and noncachaeble code read requestsmem_load_uops_l3_miss_retired.local_dramRetired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)  Supports address when precise.  Spec update: BDE70umask=0x1,period=2000003,event=0xc7fp_arith_inst_retired.scalarfp_arith_inst_retired.128b_packed_singleumask=0x2,period=100003,event=0xcaumask=0x20,period=2000003,event=0x79umask=0x4,period=2000003,event=0x80Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalledCycles with less than 2 uops delivered by the front endCounts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional regionumask=0x8,period=2000003,event=0xc8umask=0x40,period=2000003,event=0xc9umask=0x2,period=100003,event=0x3umask=0x2,period=2000003,event=0x3cbr_inst_exec.taken_conditionalThis event counts taken speculative and retired mispredicted indirect branches excluding calls and returnsumask=0x88,period=200003,event=0x89umask=0xff,period=200003,event=0x89Cycles per thread when uops are executed in port 0Cycles per core when uops are exectuted in port 0umask=0x2,any=1,period=2000003,event=0xa1uops_executed_port.port_2_coreuops_dispatched_port.port_5cycle_activity.stalls_l2_missCycles where at least 4 uops were executed per-threadNumber of times any microcode assist is invoked by HW upon uop writebackinv=1,umask=0x1,cmask=10,period=2000003,event=0xc2This event counts all (macro) branch instructions retiredThis is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired (Precise event)Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event)Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_h_requests.writes_localunc_m_pre_count.rdPre-charge for reads. Unit: uncore_imc umask=0x4,period=2000003,event=0x8Load misses that miss the  DTLB and hit the STLB (2M)This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69Number of DTLB page walker hits in the L2  Spec update: BDM69, BDM98IpCallNumber of Instructions per non-speculative Branch Misprediction (JEClear)Core actual clocks when any Logical Processor is active on the Physical Coreumask=0xc2,period=200003,event=0x24umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020001offcore_response.demand_data_rd.supplier_none.snoop_hitmoffcore_response.demand_code_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0008offcore_response.pf_l2_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0020offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwdoffcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000028000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C8000offcore_response.other.l3_hit.snoop_hitmoffcore_response.all_pf_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0240offcore_response.all_data_rd.any_responseoffcore_response.all_data_rd.supplier_none.any_snoopoffcore_response.all_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020122Randomly selected loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitmoffcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000200offcore_response.pf_l3_code_rd.l3_miss.snoop_missoffcore_response.other.l3_miss_local_dram.snoop_hitmoffcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwdA cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor coreUnit: uncore_arb Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time )Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: BDM35 (Precise event)Retired load uops misses in L1 cache as data sources  Supports address when precise (Precise event)This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)offcore_response.pf_llc_code_rd.llc_hit.any_responseoffcore_response.all_data_rd.llc_miss.remote_dramCounts prefetch (that bring data to LLC only) code reads miss in the L3Number of near branch instructions retired that were mispredicted and taken (Precise event)l2_ifetch.self.s_stateumask=0x44,period=200000,event=0x29umask=0x54,period=200000,event=0x29l2_data_rqsts.self.e_stateumask=0x48,period=200000,event=0x2cl2_ld_ifetch.self.mesiumask=0x74,period=200000,event=0x30simd_sat_uop_exec.ssimd_sat_uop_exec.arSIMD packed multiply micro-ops executedsimd_inst_retired.scalar_singleumask=0xe0,period=200000,event=0x66umask=0xe0,period=200000,event=0x68bus_trans_def.selfumask=0xe0,period=200000,event=0x70umask=0x83,period=200000,event=0x2data_tlb_misses.dtlb_missDuration of page-walks in core cyclesCounts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writebackfetch_stall.icache_fill_pending_cyclesCounts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000001000offcore_response.bus_locks.any_responseoffcore_response.pf_l2_data_rd.l2_miss.hitm_other_coreCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000002Load uops that split a page (Precise event capable) (Must be precise)Floating point divide uops retired. (Precise Event Capable) (Must be precise)Counts the number of taken branch instructions retired (Must be precise)baclears.condCounts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Floating point divide uops retired (Precise Event Capable) (Must be precise)Page walks outstanding due to a demand load every cycleCounts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultDemand Data Read requests  Spec update: HSD78Miss in last-level (L3) cache. Excludes Unknown data-source  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)Any MLC or L3 HW prefetch accessing L2, including rejectsoffcore_response.demand_rfo.l3_hit.hit_other_core_no_fwdCounts cycles MITE is delivered at least one uop. Set Cmask = 1Randomly selected loads with latency value being above 4  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 32  Spec update: HSD76, HSD25, HSM26 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400002umask=0x1,edge=1,period=100003,cmask=1,event=0x5cCounts all near executed branches (not necessarily retired)Cycles where at least 3 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31umask=0x84,event=0x22umask=0x88,event=0x22Store miss in all TLB levels causes a page walk that completes. (4K)Number of ITLB page walker hits in the L2Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400004Counts the number of not taken branch instructions retiredAll retired load uops. (Precise Event)mem_load_uops_llc_hit_retired.xsnp_missClean L2 cache lines evicted by the MLC prefetcheroffcore_response.all_rfo.llc_hit.no_snoop_neededoffcore_response.demand_code_rd.llc_hit.any_responsesimd_fp_256.packed_singleumask=0xc,period=2000003,event=0xa1umask=0xc,any=1,period=2000003,event=0xa1Cycles per thread when load or STA uops are dispatched to port 3unc_cbo_cache_lookup.mRetired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820004offcore_response.demand_data_rd.llc_miss.remote_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800010Write requests to home agent. Unit: uncore_ha Cycles where transmitting QPI link is in half-width mode. Unit: uncore_qpi event=0xbfreq_ge_2000mhz_cycles %(unc_p_freq_ge_4000mhz_cycles / unc_p_clockticks) * 100.Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cacheThis event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-endCounts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excludedother_assists.itlb_miss_retiredumask=0x1,period=100003,event=0x3unc_m_act_countCounts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_code_rd.outstandingoffcore_response.any_code_rd.l2_hit_far_tile_e_foffcore_response.any_data_rd.l2_hit_far_tile_e_fCounts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeCounts Demand cacheable data and L1 prefetch data read requests  that accounts for any responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000408000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800408000Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.pf_l1_data_rd.l2_hit_far_tile_e_fCounts L1 data HW prefetches that accounts for any responseoffcore_response.pf_software.l2_hit_far_tile_e_foffcore_response.uc_code_reads.l2_hit_far_tile_moffcore_response.partial_writes.l2_hit_far_tile_mCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_l2_code_rd.l2_hit_near_tile_e_fCounts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_data_rd.l2_hit_this_tile_mCounts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_software.l2_hit_this_tile_mCounts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E stateCounts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_pf_l2.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000070offcore_response.any_read.mcdram_nearoffcore_response.pf_l1_data_rd.mcdram_nearCounts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit farCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.partial_writes.ddr_farCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Localoffcore_response.partial_reads.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400040offcore_response.demand_code_rd.mcdram_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01818032f7L1D cache lines allocated in the M statel1d.m_snoop_evictl1d_cache_ld.m_statel1d_cache_lock.s_stateumask=0x4,period=200000,event=0x4eL2 data demand loads in I state (misses)l2_data_rqsts.prefetch.mesiumask=0x20,period=200000,event=0x24umask=0x20,period=10000,event=0xfLoad instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)Offcore code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.any_ifetch.remote_cache_dramOffcore code reads that HITM in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFFFFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x47FFOffcore writebacks that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x177offcore_response.data_in.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3803Offcore demand data reads that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x104Offcore demand code reads satisfied by the LLC and not found in a sibling coreOffcore prefetch data requests satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_data.remote_cacheOffcore prefetch data reads satisfied by any cache or DRAMOffcore prefetch data reads satisfied by the IO, CSR, MMIO unitOffcore prefetch data reads satisfied by the LLC and not found in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F20Offcore prefetch requests satisfied by a remote cacheoffcore_response.prefetch.remote_cache_dramumask=0x1,period=2000000,event=0xccSIMD integer 64 bit unpack operationsOffcore code reads that missed the LLCOffcore code or data read requests that missed the LLCoffcore_response.data_in.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4003Offcore prefetch data requests satisfied by the local DRAMoffcore_response.pf_ifetch.any_llc_missLate Branch Prediction Unit clearsumask=0x2,period=100000,event=0xb8cpu_clk_unhalted.total_cyclesumask=0x1,period=2000000,event=0x20ssex_uops_retired.packed_doubleCycles no Uops issued on any port (core count)umask=0x20,period=2000000,event=0xb1period=200003,umask=0x27,event=0x24offcore_response.demand_code_rd.l3_hit_s.snoop_nonemem_inst_retired.all_storesoffcore_response.demand_code_rd.l4_hit_local_l4.spl_hitperiod=200003,umask=0xf8,event=0x24offcore_response.demand_rfo.l3_hit_m.spl_hitoffcore_response.demand_code_rd.l3_hit.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00401C0004Counts the total number of L2 code requestsoffcore_response.other.l3_hit_m.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040020002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100001Counts both cacheable and non-cacheable code read requestsCounts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)offcore_response.demand_rfo.l3_hit_e.snoop_missNumber of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementicache_16b.ifdata_stallperiod=2000003,umask=0x4,event=0x79frontend_retired.l2_missCycles where a code fetch is stalled due to L1 instruction cache tag missCounts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event)cmask=1,period=2000003,umask=0x10,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x402006period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000028000offcore_response.demand_code_rd.l3_miss.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x203C400002offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rdCounts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise (Must be precise)period=2000003,umask=0x1,event=0xc8sw_prefetch_access.ntaCounts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this caseperiod=400009,event=0xc5Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issuesany=1,period=2000003,event=0x3cperiod=100007,umask=0x1,event=0xaeperiod=100003,umask=0x1,event=0x8Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000040umask=0x3f,period=200003,event=0xcaTotal page walks that are completed (I-side and D-side)Counts all prefetch code reads that hit in the LLCCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0200offcore_response.all_pf_data_rd.llc_miss.dramoffcore_response.data_in_socket.llc_miss_local.any_llc_hitMispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event)Outstanding offcore demand code readsoffcore_requests_outstanding.demand.rfoumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5044REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAMREQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAMREQUEST = ANY RFO and RESPONSE = ANY_LOCATIONumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f03REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATIONoffcore_response.other.local_dram_and_remote_cache_hitREQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATIONREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITMoffcore_response.pf_data_rd.local_dram_and_remote_cache_hitREQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf811REQUEST = DATA_IN and RESPONSE = REMOTE_DRAMoffcore_response.other.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3040REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISSumask=0x80,period=200000,event=0x85offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwdoffcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0120Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedOFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0400offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwdfp_arith_inst_retired.512b_packed_singleperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000004Counts demand data reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cacheidi_misc.wb_upgradeTotal number of retired Instructions, Sample with: INST_RETIRED.PREC_DISTLLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha PCI Express bandwidth writing at IIO, part 0. Unit: uncore_iio umask=0x01,event=0x53umask=0x01,event=0x54Number of times that an RFO hit in S state. Unit: uncore_cha Ingress (from CMS) Request Queue Rejects; PhyAddr Match. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data: Part 3. Unit: uncore_iio unc_iio_data_req_by_cpu.peer_read.part1Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busPeer to peer read request for 4 bytes made by IIO Part1 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x83unc_iio_txn_req_by_cpu.mem_read.part3fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x84unc_iio_txn_req_of_cpu.mem_write.part1Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busPCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cacheunc_i_coherent_ops.rfoOccupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRPInbound write (fast path) requests received by the IRP. Unit: uncore_irp Messages sent direct to core (bypassing the CHA). Unit: uncore_m2m Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabledunc_m2m_directory_lookup.anyCounts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid)AD Egress (to CMS) Occupancy. Unit: uncore_m2m unc_upi_txl_flits.idleRetired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event  Supports address when precise (Precise event)offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040120offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020120This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_m.hit_other_core_no_fwdoffcore_response.all_reads.l3_hit_s.snoop_noneoffcore_response.all_rfo.l3_hit_e.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080122offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwdoffcore_response.all_rfo.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100122This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_m.hitm_other_coreoffcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoopoffcore_response.demand_code_rd.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080002offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoopThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISSoffcore_response.other.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800108000offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200080offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwdoffcore_response.pf_l3_rfo.l3_hit_m.no_snoop_neededidq.dsb_uops / (idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops)Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetchesOCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss.remote_hitmocr.all_pf_rfo.l3_miss_local_dram.hitm_other_coreocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwdocr.all_reads.l3_miss.remote_hit_forwardOCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOPOCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDOCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_code_rd.l3_miss_local_dram.snoop_missCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwdCounts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000400ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISSCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISSocr.pf_l3_data_rd.l3_miss.remote_hit_forwardCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l3_rfo.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.all_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_coreOCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISSOCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_s.snoop_noneOCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONEOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_f.snoop_noneocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwdOCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_pf_rfo.supplier_none.snoop_noneocr.all_reads.l3_hit_f.hit_other_core_fwdocr.all_rfo.l3_hit_f.hit_other_core_no_fwdocr.all_rfo.l3_hit_s.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOPocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_neededocr.demand_code_rd.supplier_none.hit_other_core_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISSocr.demand_data_rd.l3_hit.snoop_noneocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwdocr.demand_data_rd.l3_hit_s.hitm_other_coreocr.demand_data_rd.supplier_none.any_snoopocr.demand_rfo.l3_hit_m.hit_other_core_fwdocr.demand_rfo.l3_hit_s.hit_other_core_no_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.demand_rfo.supplier_none.hit_other_core_fwdCounts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDEDCounts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWDocr.other.l3_hit_s.no_snoop_neededocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwdocr.pf_l1d_and_sw.l3_hit_m.snoop_missCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit.hit_other_core_fwdocr.pf_l2_data_rd.l3_hit_f.any_snoopocr.pf_l2_data_rd.l3_hit_f.snoop_noneCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.pf_l2_rfo.l3_hit_s.snoop_noneocr.pf_l3_rfo.l3_hit.snoop_missCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l3_rfo.supplier_none.snoop_missUnderfill readsTag Check; CleanCounts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesperiod=1000003,umask=0x1,event=0x60Counts the cycles for which the thread is active and the superQ cannot take any more entriesCounts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesCounts retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event)Counts retired store instructions that true miss the STLB  Supports address when precise (Precise event)period=100003,umask=0x2,event=0xc1Counts the number of times HLE abort was triggeredperiod=100003,umask=0x4,event=0x5dCounts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionocr.streaming_wr.l3_missocr.demand_rfo.l3_hit.snoop_hitmCounts streaming stores that DRAM supplied the requestCounts hardware prefetch data reads (which bring data to L2)  that have any type of responsetopdown.slotsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0001ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwdCounts the number of uops delivered to the back-end by the LSD(Loop Stream Detector)Cycle counts are evenly distributed between active threads in the Coreperiod=100003,umask=0x20,event=0x8Cycles the queue waiting for offcore responses is full2LM Tag Check : Hit in Near Memory Cache. Unit: uncore_imc DRAM Precharge commands. : Precharge due to read. Unit: uncore_imc umask=0x08,event=0xeaPMM Write Pending Queue Occupancy. Unit: uncore_imc unc_cha_tor_inserts.ia_hit_drdTOR Inserts : All requests from IO Devices that missed the LLC. Unit: uncore_cha TOR Occupancy : CRds issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha TOR Inserts : CLFlushes issued by iA Cores. Unit: uncore_cha Cache and Snoop Filter Lookups; Data Read Request. Unit: uncore_cha fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0x83fc_mask=0x07,ch_mask=0x10,umask=0x80,event=0x83unc_iio_data_req_of_cpu.cmpd.part5fc_mask=0x07,ch_mask=0x40,umask=0x80,event=0x83unc_iio_txn_req_by_cpu.mem_read.part4unc_iio_txn_req_of_cpu.mem_write.part5unc_i_misc1.lost_fwdevent=0x17Counts cacheable memory requests that miss in the the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Counts requests to the Instruction Cache (ICache) for one or more bytes cache LineCounts reference cycles (at TSC frequency) when core is not halted.  This event uses a programmable general purpose perfmon counterCounts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis(cycles / cpu_clk_unhalted.ref_tsc) * msr@tsc@ / 1000000000 ocr.demand_data_rd.l3_miss_localCounts the number of unhalted cycles a core is blocked due to an accepted lock issued by other coresperiod=200003,umask=0x7e,event=0xc4period=2000003,umask=0x1,event=0xc2Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event)Counts the number of page walks completed due to load DTLB misses to a 2M or 4M pageCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page faultCounts the number of page walks completed due to store DTLB misses to a 4K pageCounts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBThe number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely eventl2_request_g1.rd_blk_xumask=0x40,event=0x60All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sizedCore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types)event=0xc4ex_ret_brn_farThe number of near return instructions (RET or RET Iw) retireddram_channel_data_controller_0The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Opsumask=0x40,event=0x3umask=0x01,event=0x4Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailablebranch_predictionl2_cache_accesses_from_dc_missesumask=0x70,event=0x64l2_dtlb_missesbp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_missic_tag_hit_miss.all_instruction_cache_accessesL1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLBde_dis_dispatch_token_stalls2.int_sch0_token_stallLS_MICROARCHITECTURAL_LATE_CANCELNB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENTPC_BRANCH_MIS_PREDPMUEXTIN0_EVTEVENT_04HEVENT_0AHEVENT_11HEVENT_18HEVENT_1DHEVENT_88HEVENT_C8HEVENT_D3HINST_RETIREDUNALIGNED_LD_SPECIMPRECISE_SETBOUNDSL2CACHE_EVICTL2CACHEMASTER_READ_RSPRF_STALLDSPRAM_STALL_CYCLESEJTAG_DTRIGGERIFU_REPLAYSIFU_IDU_NO_FETCH_CYCLESUNCACHED_LOAD_INSNSSYSTEM_EVENT_7CCFP_STORE_CAUSES_STALL_IN_LSUFP_THREE_QUARTERS_FPSCR_RENAMES_BUSYFP_DENORMALIZED_RESULTDISPATCHES_TO_FPR_ISSUE_QUEUEREFETCH_SERIALIZATIONVPU_MARKED_INSTR_COMPLETEDFXU0_IDLE_FXU1_IDLEMARKED_STORE_SENT_TO_STSADDRESS_COLLISIONINSTR_MMU_TLB4K_RELOADSBIU_MASTER_RETRIESEXT_INPUT_INTR_TAKENL2_CACHE_LOCKSDVT2_DETECTEDsharedIAFMIPS_BERITHREADpmc_pmu_event_get_by_idxname: %s
l3cache%s, "pmcid": "0x%08x", "pid": "%d", "tid": "%d", "cpuflags": "0x%08x", "cpuflags2": "0x%08x", "pc": [ v24GenuineIntel-6-6ACycles Per Instruction (threaded)InstructionsAverage Branch Address Clear Cost (fraction of cycles)1 - cpu_clk_thread_unhalted.one_thread_active / ( cpu_clk_thread_unhalted.ref_xclk_any / 2 ) if #smt_on else 0Demand Data Read miss L2, no rejectsl2_rqsts.code_rd_hitmem_uops_retired.stlb_miss_storesumask=0x41,period=100003,event=0xd0mem_uops_retired.split_storesThis is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement  Supports address when precise (Precise event)umask=0x1,period=2000003,event=0xd1umask=0x40,period=100003,event=0xd1This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_miss_retired.remote_fwdNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementInstruction Decode Queue (IDQ) empty cyclesumask=0x4,period=2000003,event=0x79This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQUops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyCycles where a code fetch is stalled due to L1 instruction-cache missThis event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3idq_uops_not_delivered.cycles_le_2_uop_deliv.coreSpeculative cache line split STA uops dispatched to L1 cachetx_exec.misc2Number of times HLE commit succeededNumber of times RTM abort was triggered (PEBS) (Precise event)mem_trans_retired.load_latency_gt_8This event counts the unhalted core cycles during which the thread is in the ring 0 privileged modeThis event counts when there is a transition from ring 1,2 or 3 to ring0umask=0x40,period=2000003,event=0xeNumber of Multiply packed/scalar single precision uops allocatedNumber of integer Move Elimination candidate uops that were not eliminatedumask=0x8,period=1000003,event=0x58This event counts taken speculative and retired indirect calls including both register and memory indirectbr_inst_exec.all_indirect_jump_non_call_retumask=0x2,period=2000003,event=0xa1Counts number of cycles nothing is executed on any execution portNumber of uops to be executed per-thread each cycleCycles where at least 1 uop was executed per-threadbr_inst_retired.near_callumask=0x2,period=100007,event=0xc4rob_misc_events.lbr_insertsumask=0x11,event=0x34,filter_state=0x1umask=0x3,event=0x35,filter_opc=0x182uncore_haread requests to local home agent. Unit: uncore_ha unc_h_requests.reads_remoteumask=0x20,event=0x21PCU clock ticks. Use to get percentages of PCU cycles events. Unit: uncore_pcu umask=0xe,period=100003,event=0x8Cycles when PMH is busy with page walks  Spec update: BDM69This event counts the number of cycles while PMH is busy with the page walk  Spec update: BDM69itlb_misses.walk_completed_4kPer-Logical Processor actual clocks when the Logical Processor is activeInstruction per (near) call (lower number means higher occurance rate)Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)offcore_response.demand_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0004offcore_response.corewb.any_responseCounts prefetch (that bring data to L2) data readsoffcore_response.pf_l2_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0020offcore_response.pf_l3_rfo.l3_hit.any_snoopoffcore_response.all_pf_data_rd.supplier_none.any_snoopoffcore_response.all_pf_rfo.supplier_none.any_snoopoffcore_response.all_pf_code_rd.supplier_none.snoop_noneRandomly selected loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_data_rd.supplier_none.snoop_non_dramoffcore_response.demand_rfo.l3_miss.snoop_noneoffcore_response.demand_code_rd.l3_miss.snoop_not_neededoffcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000040offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000120offcore_response.all_pf_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000091umask=0x1,edge=1,period=100007,cmask=1,event=0x5cumask=0x1,period=2000003,cmask=1,event=0xb1L3 Lookup any request that access cache and found line in I-stateunc_cbo_cache_lookup.read_mesiRetired load uops that miss the STLB  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000091(unc_m_power_channel_ppd / unc_m_clockticks) * 100.Cycles L2 address bus is in useumask=0x70,period=200000,event=0x24umask=0x78,period=200000,event=0x2eRetired loads that miss the L2 cachesimd_uop_type_exec.pack.ssimd_instr_retireddecode_stall.pfb_emptydecode_stall.iq_fullmacro_insts.cisc_decodedprefetch.software_prefetch.arbus_trans_def.all_agentsumask=0xe0,period=200000,event=0x6esnoop_stall_drv.selfumask=0x0,period=2000000,event=0x3cCore cycles when core is not haltedcpu_clk_unhalted.coreAll macro conditional branch instructionsbr_inst_type_retired.uncondAll non-indirect callsuops_retired.stalled_cyclesCycles issue is stalled due to div busyRetired loads that miss the DTLB (precise event) (Precise event)l2_reject_xq.allCounts the number of store uops retired  Supports address when precise (Must be precise)Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000048000Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cacheoffcore_response.partial_streaming_stores.l2_hitCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000800Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)ms_decoded.ms_entryfetch_stall.itlb_fill_pending_cyclesReference cycles when core is not halted  (Fixed event)uops_retired.fpdivumask=0x7e,period=200003,event=0xc4Retired conditional branch instructions (Precise event capable) (Must be precise)br_inst_retired.callumask=0x0,period=200003,event=0xc5cycles_div_busy.allumask=0x3,period=200003,event=0x5Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.outstandingCounts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedumask=0x1,period=20003,event=0xc3Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultSTLB flushesOffcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61Counts all prefetch (that bring data to LLC only) data reads hit in the L3Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cyclesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00040This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP)This event counts cycles during which no instructions were executed in the execution stage of the pipelineNumber of uops executed on the core  Spec update: HSD30, HSM31umask=0x28,event=0x34Number of DTLB page walker loads that hit in the L1+FBData from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event)Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: HSM30 (Precise event)offcore_response.pf_llc_data_rd.llc_miss.any_responseedge=1,umask=0x1,cmask=1,period=100003,event=0x5cNumber of microcode assists invoked by HW upon uop writebackNot rejected writebacks from L1D to L2 cache lines in M stateumask=0x4,period=100003,event=0xf2umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0244umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010122Counts all data/code/rfo references (demand & prefetch)fp_comp_ops_exe.sse_packed_double( (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / 1000000000 ) / duration_timeumask=0x1,period=100003,event=0xbeCounts demand code reads that miss the LLC and the data returned from dramIncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this coreUnit: uncore_cbox A snoop invalidates a non-modified line in some processor coreA snoop hits a modified line in some processor coreumask=0x10,event=0x34Filter on processor core initiated cacheable write requestsunc_cbo_cache_lookup.extsnp_filterUnit: uncore_arb Counts the number of LLC evictions allocatedCycles PMH is busy with this walkoffcore_response.all_data_rd.llc_hit.snoop_missoffcore_response.pf_l2_data_rd.llc_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) code reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800244Counts demand data reads that miss the LLC  and the data returned from local dramCounts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc20002umask=0x1,event=0x35,filter_opc=0x19cevent=0xdMemory page conflicts. Unit: uncore_imc event=0xe,filter_band3=40unc_p_freq_ge_1200mhz_transitionsumask=0x20,period=2000003,event=0x59This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache missesoffcore_response.any_pf_l2.l2_hit_near_tile_moffcore_response.any_rfo.l2_hit_near_tile_e_fCounts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.partial_reads.l2_hit_far_tile_e_foffcore_response.partial_reads.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400040umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400001offcore_response.bus_locks.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000200offcore_response.any_request.l2_hit_this_tile_foffcore_response.pf_software.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400070Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200022umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800200Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far)offcore_response.bus_locks.mcdramCounts any Prefetch requests that accounts for responses from MCDRAM (local and far)offcore_response.pf_software.ddrCounts the number of mispredicted near RET branch instructions retired (Precise event)no_alloc_cycles.mispredictsCounts the total number of instructions retiredCounts the total page walks that are completed (I-side and D-side)Cycles L1D and L2 lockedl1d_cache_lock.m_statel1d_cache_lock_fb_hitumask=0x8,period=2000000,event=0x41umask=0x2,period=200000,event=0x26L2 modified lines evicted by a demand requestumask=0x4,period=100000,event=0xf2l2_rqsts.prefetch_missumask=0x80,period=200000,event=0x24mem_load_retired.l1d_hitMemory instructions retired above 1024 clocks (Precise Event)offcore_response.any_data.llc_hit_other_core_hitoffcore_response.any_ifetch.local_cache_dramoffcore_response.any_rfo.local_cacheoffcore_response.corewb.remote_cache_dramoffcore_response.data_ifetch.local_cache_dramoffcore_response.data_ifetch.remote_cache_dramoffcore_response.data_in.io_csr_mmioOffcore request = all data, response = local cache or dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4703offcore_response.demand_ifetch.io_csr_mmioOffcore demand RFO requests satisfied by the LLC and HIT in a sibling coreOffcore other requests satisfied by any cache or DRAMOffcore other requests satisfied by a remote cacheAll offcore prefetch data requestsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x730All offcore prefetch data readsOffcore prefetch data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_rfo.llc_hit_other_core_hitoffcore_response.pf_rfo.llc_hit_other_core_hitmOffcore prefetch RFO requests that HITM in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x270offcore_response.prefetch.remote_cache_hitmSIMD integer 64 bit shift operationsumask=0x1,period=2000000,event=0xd0umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF8FFOffcore writebacks that missed the LLCOffcore code or data read requests satisfied by the local DRAMOffcore prefetch code reads satisfied by the local DRAMoffcore_response.pf_ifetch.remote_dramoffcore_response.pf_rfo.remote_dramload_dispatch.rsFlag stall cyclesumask=0x2,period=2000000,event=0xd2Retired branch instructions (Precise Event)Total CPU cyclesumask=0xf,period=2000000,event=0x87Stall cycles due to BPU MRU bypassInstructions retired (Programmable counter and Precise Event) (Precise event)umask=0x40,period=2000000,event=0xa2umask=0x4,period=2000000,event=0xa2Uops executed on port 5umask=0x1,period=2000000,cmask=1,event=0xc2itlb_misses.anyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400408000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080002Counts retired load instructions with at least one uop that missed in the L3 cache  Supports address when precise (Precise event)Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSperiod=200003,umask=0x3f,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020002period=100003,umask=0x8,event=0xd2period=2000003,umask=0x81,event=0xd0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0100001offcore_response.other.l3_hit_e.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100004offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwdmem_inst_retired.split_loadsoffcore_response.demand_data_rd.l3_hit_e.snoop_not_neededOffcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycleperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020001Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetchesNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementfrontend_retired.latency_ge_128Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITERetired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Must be precise)frontend_retired.latency_ge_4period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000100002period=100007,umask=0x1,event=0xcd,ldlat=0x20period=2000003,umask=0x10,event=0xc9period=100003,umask=0x2,event=0xc3Counts cycles during which no uops were dispatched from the Reservation Station (RS) per threadperiod=100003,umask=0x1,event=0x7Counts the number of x87 uops executedCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4period=2000003,umask=0x20,event=0xa1cmask=1,inv=1,period=2000003,umask=0x1,event=0xeThis event counts return instructions retired  Spec update: SKL091 (Precise event)cmask=1,period=2000003,umask=0x1,event=0xb1Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)inst_retired.any / ( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )Memory_BW;OffcoreHPC;Memory_BW;SoCCounts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultperiod=100003,umask=0x20,event=0x85period=2000003,umask=0x10,event=0x4fThis event counts requests originating from the core that references a cache line in the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000044Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss responseCounts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss responseCounts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedStalls due to Memory orderingumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0120offcore_response.all_pf_rfo.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.pf_l2_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400200umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f11REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff08REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITMoffcore_response.data_ifetch.local_dram_and_remote_cache_hitREQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHEumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f10umask=0x1,period=100000,event=0xb7,offcore_rsp=0x40ffumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf803offcore_response.demand_rfo.other_local_dramoffcore_response.pf_rfo.other_local_dramumask=0x80,period=200000,event=0x8itlb_misses.walk_cyclesperiod=100007,umask=0x2,event=0xd3Counts all demand & prefetch RFOs that have any response typeCounts all demand & prefetch RFOs that hit in the L3offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwdoffcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwdoffcore_response.pf_l3_rfo.l3_hit.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000122offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdoffcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwdoffcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000400Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cacheCounts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000080offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forwardperiod=200003,umask=0x7,event=0x28period=200003,umask=0x40,event=0x28MemoryBound;MemoryBWCounts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller).  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) commandunc_cha_requests.reads_remoteunc_iio_data_req_of_cpu.mem_write.part3unc_cha_dir_lookup.no_snpCounts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)unc_cha_rxc_irq1_reject.pa_matchumask=0x01,event=0x3dunc_iio_comp_buf_inserts.cmpd.part1unc_iio_data_req_by_cpu.peer_read.part0Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busPeer to peer read request for 4 bytes made by a different IIO unit to IIO Part2. Unit: uncore_iio Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_read.part1unc_iio_txn_req_by_cpu.peer_write.part1Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_m2m_directory_update.anyumask=0x4,event=0x37umask=0x10,event=0x38This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080120offcore_response.all_pf_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10002007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02002007F7offcore_response.all_reads.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800407F7offcore_response.all_reads.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000407F7offcore_response.all_reads.supplier_none.no_snoop_neededoffcore_response.all_rfo.l3_hit_e.hit_other_core_fwdoffcore_response.all_rfo.l3_hit_f.hit_other_core_fwdoffcore_response.all_rfo.l3_hit_f.snoop_noneoffcore_response.all_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200004offcore_response.demand_code_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.demand_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C8000offcore_response.other.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80408000offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwdoffcore_response.pf_l1d_and_sw.l3_hit_s.any_snoopoffcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200020offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwdoffcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020080This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_f.any_snoopoffcore_response.pf_l3_rfo.l3_hit_s.any_snoopoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_neededLSD_Coverageperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000490OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONEocr.all_pf_rfo.l3_miss_local_dram.any_snoopocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdOCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_miss.snoop_missOCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss.hitm_other_coreCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000004Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORECounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_rfo.l3_miss.hitm_other_coreCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISSCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804008000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000400ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000010ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_noneocr.pf_l2_rfo.l3_miss.remote_hit_forwardocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORECounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss_local_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000080ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.all_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONEoffcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwdoffcore_response.pf_l2_data_rd.l3_miss.no_snoop_neededoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_f.snoop_noneocr.all_data_rd.l3_hit_s.hit_other_core_no_fwdOCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISSocr.all_pf_data_rd.l3_hit_e.any_snoopOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDOCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOPOCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDEDOCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISSocr.all_reads.l3_hit_f.hitm_other_coreocr.all_reads.l3_hit_m.no_snoop_neededocr.all_reads.l3_hit_s.hit_other_core_no_fwdOCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_rfo.l3_hit_f.any_snoopOCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.demand_code_rd.l3_hit_e.hit_other_core_fwdocr.demand_code_rd.l3_hit_s.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.demand_data_rd.l3_hit_f.hit_other_core_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOPocr.demand_rfo.l3_hit_f.snoop_missCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOPCounts any other requests  OCR.OTHER.SUPPLIER_NONE.ANY_SNOOPocr.pf_l2_data_rd.l3_hit.hitm_other_coreCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit.snoop_missocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwdocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwdocr.pf_l2_rfo.l3_hit.hitm_other_coreocr.pf_l2_rfo.l3_hit_e.snoop_missocr.pf_l3_data_rd.l3_hit_e.hitm_other_coreocr.pf_l3_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISSCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONECounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDEDRegular reads(RPQ) commands for Intel Optane DC persistent memory. Unit: uncore_imc umask=0x2,event=0xd3period=200003,umask=0x2,event=0xd1Counts retired load instructions with locked access  Supports address when precise (Precise event)cmask=1,edge=1,period=1000003,umask=0x2,event=0x48period=100003,umask=0x40,event=0xc7period=100003,umask=0x2,event=0xc7Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)ocr.other.local_dramocr.demand_rfo.l3_hit.snoop_hit_no_fwdCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)Number of instructions retired. Fixed Counter - architectural event (Precise event)Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stallCounts cycles when at least 3 micro-ops are executed from any thread on physical coreFor every cycle where the core is waiting on at least 1 outstanding data read request, increments by 1.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor1 - cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_distributed if #smt_on else 0umask=0x10,event=0xd3unc_m_rpq_occupancy_pch0TOR Inserts : RFOs issued by iA Cores that Hit the LLC. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts; WCiL misses from local IA. Unit: uncore_cha unc_iio_txn_req_of_cpu.cmpd.part2fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0xc0fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0xc1unc_iio_comp_buf_inserts.cmpd.part4unc_iio_comp_buf_inserts.cmpd.all_partsfc_mask=0x04,ch_mask=0xff,umask=0x03,event=0xc2: All Inserts Inbound (p2p + faf + cset). Unit: uncore_irp Multi-socket cacheline Directory Lookups : Found in S state. Unit: uncore_m2m umask=0x01,event=0x2cTag Hit : Clean NearMem Read Hit. Unit: uncore_m2m M2M Reads Issued to iMC : PMM - All Channels. Unit: uncore_m2m itlb.fillsmem_bound_stalls.load_l2_hitCounts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uopsCounts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARSCounts the number of issue slots every cycle that were not delivered by the frontend due to decode stallsCounts the number of Extended Page Directory Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesbp_dyn_ind_predumask=0x02,event=0x60l2_pf_hit_l2Retired Taken Branch Instructionsex_ret_brn_tkn_mispThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)umask=0x02,event=0xcbRetired Conditional Branch InstructionsDiv Cycles Busy countThe number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3umask=0x02,event=0x847The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1umask=0x0f,event=0fp_ret_sse_avx_ops.dp_div_flopsumask=0xff,event=0x45L1 DTLB Reload of a page of 32K sizeumask=0x08,event=0x46ls_tablewalker.dsidels_pref_instr_disp.store_prefetch_wumask=0x04,event=0xafL2 Cache Misses from L1 Instruction Cache MissesTotal number uOps assigned to pipe 2x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retiredRetired lock instructions. High speculative cacheable lock speculation succeededSoftware Prefetch Data Cache Fills by Data Source. From another cache (home node local)umask=0x40,event=0x5als_hw_pf_dc_fill.ls_mabresp_rmt_cacheumask=0x10,event=0xaeDispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedls_any_fills_from_sys.int_cacheAny Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_any_fills_from_sys.lcl_l2L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLBls_sw_pf_dc_fills.ext_cache_localSoftware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same nodels_hw_pf_dc_fills.ext_cache_localumask=0xff,event=0x78Any FP dispatch. Types of Oops Dispatched from DecoderL1 Data Cache Fills: AllMacro-ops DispatchedFP_DISPATCHED_FPU_FAST_FLAG_OPSDC_MISALIGNED_DATA_REFERENCEFR_DISPATCH_STALL_WHEN_FPU_IS_FULLITLB_REFILLEXC_EXECUTEDBUS_CYCLESPMUEXTIN_EVTEVENT_5AHEVENT_63HEVENT_D5HJAVA_BYTECODECID_WRITE_RETIREDLDST_SPECEXC_TRAP_DABORTLL_CACHE_RDL2CACHE_READ_MISSL2CACHEMASTER_READ_REQUNCACHED_BLOCK_CYCLESFETCH_BUFFER_ALLOCATEDFSB_FULL_PIPELINE_STALLSDCACHE_LOAD_ACCESSESLOAD_STORE_NO_FILL_REQUESTSBADDTLB_BIT_TRANSITIONSUNRESOLVED_BRANCHESSC_INSTR_COMPLETEDLSU_LOAD_VS_STORE_QUEUE_ALIAS_STALLDST_STREAM_1_CACHE_LINE_FETCHESGPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLDFOLDED_BRANCHESFXU_COMPLETION_STALLBUS_LOWFINISHED_UNCOND_BRANCHES_MISS_BTBLOADS_TRANSLATEDL2_CACHE_DATA_ALLOCATIONSSTWCX_SUCCESSESinterruptsinvalidmemory-controller-lo-pri-bypassREADPRECISEP5metric_expr: %s
UNHALTED_CORE_CYCLES=v20GenuineIntel-6-A[56]AuthenticAMD-25-[[:xdigit:]]+inst_retired.anySMTKernel_Utilizationl2_rqsts.l2_pf_missl2_rqsts.missL2 cache hits when fetching instructions, code readsRetired store uops that miss the STLB. (Precise Event - PEBS)  Supports address when precise (Precise event)mem_load_uops_retired.l3_missNumber of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_assist.x87_outputThis event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1idq_uops_not_delivered.cycles_le_1_uop_deliv.coretx_exec.misc3machine_clears.memory_orderingumask=0x8,period=2000003,event=0xc9Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details)This event counts loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)Reference cycles when the core is not in halt stateumask=0x3,cmask=1,period=2000003,event=0xduops_issued.stall_cyclesuops_issued.slow_leaThread cycles when thread is not in halt statecpu_clk_unhalted.thread_p_anycpu_clk_unhalted.one_thread_activeload_hit_pre.hw_pfbr_inst_exec.nontaken_conditionalThis event counts both taken and not taken speculative and retired mispredicted branch instructionsThis event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3umask=0x1,period=2000003,event=0xa2Counts number of cycles the CPU has at least one pending  demand* load request missing the L2 cacheumask=0x4,cmask=4,period=2000003,event=0xa3Total execution stallsExecution stalls while memory subsystem has an outstanding loadCounts number of cycles the CPU has at least one pending  demand load request missing the L1 data cachelsd.cycles_activeuops_executed.threadumask=0x2,cmask=1,period=2000003,event=0xb1uops_executed.core_cycles_ge_4umask=0x2,period=2000003,event=0xc0other_assists.any_wb_assistmachine_clears.smcumask=0x8,period=100007,event=0xc4umask=0x20,period=400009,event=0xc4number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event)unc_c_llc_lookup.anyMMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox umask=0x3,event=0x36,filter_opc=0x182llc_misses.mem_writeevent=0x85Cycles Memory is in self refresh power mode. Unit: uncore_imc umask=0x4,event=0x2unc_p_power_state_occupancy.cores_c0dtlb_store_misses.stlb_hit_4kitlb_misses.walk_completed_1gumask=0x11,period=2000003,event=0xbcpage_walker_loads.dtlb_l2umask=0x20,period=100007,event=0xbdBranch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020004offcore_response.demand_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0008offcore_response.pf_l2_code_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0100offcore_response.pf_l3_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020090offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0240Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementumask=0x1,period=2000003,cmask=1,event=0x9coffcore_response.demand_data_rd.l3_miss.snoop_noneoffcore_response.corewb.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0020offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwdoffcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000100offcore_response.other.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000090offcore_response.all_pf_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000120offcore_response.all_pf_code_rd.l3_miss.snoop_noneoffcore_response.all_pf_code_rd.l3_miss.snoop_missoffcore_response.all_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000122umask=0x1,period=2000003,cmask=4,event=0xb1A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor coreunc_cbo_cache_lookup.write_esRetired load uops that split across a cacheline boundary  Supports address when precise (Precise event)This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)offcore_response.all_data_rd.llc_miss.remote_hitmumask=0x40,period=200000,event=0x21umask=0x44,period=200000,event=0x28l2_ld.self.demand.i_stateumask=0x71,period=200000,event=0x2el2_rqsts.self.prefetch.m_statel2_rqsts.self.demand.i_statel2_rqsts.self.demand.mesil2_reject_busq.self.any.s_stateumask=0x10,period=200000,event=0x40umask=0x20,period=2000000,event=0xb3umask=0x0,period=200000,event=0x61ext_snoop.this_agent.hitumask=0xff,period=200000,event=0x3Mispredicted cond branch instructions retiredbr_missp_type_retired.cond_takenRetired branch instructions that were predicted takenumask=0x0,period=200003,event=0x31Requests rejected by the L2QCycles code-fetch stalled due to an outstanding ICache missRequires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts memory uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)mem_uops_retired.allumask=0x1,period=200003,event=0xd1Loads retired that hit WCB (Precise event capable)  Supports address when precise (Must be precise)offcore_response.any_read.l2_miss.hitm_other_coreCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003091Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040800Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040020offcore_response.demand_code_rd.l2_miss.anyCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000002umask=0x0,period=200003,event=0xcaumask=0x1,period=200003,event=0xcaCounts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0)Reference cycles when core is not halted.  This event uses a programmable general purpose performance counterCounts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load addressbr_inst_retired.non_return_indumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010001Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.outstandingumask=0x4,period=20003,event=0xc3Page walk completed due to a demand data store to a 2M or 4M pageCounts the number of store RFO requests that miss the L2 cacheRetired load uops misses in L1 cache as data sources  Spec update: HSM30.  Supports address when precise (Precise event)offcore_response.all_requests.l3_hit.any_response Spec update: HSD56, HSM57 (Precise event)Counts demand data reads miss the L3 and the data is returned from local dramNumber of integer move elimination candidate uops that were eliminatedExecution stalls due to L1 data cache miss loads. Set Cmask=0CHUnit: uncore_cbox L3 Lookup external snoop request that access cache and found line in I-statepage_walker_loads.itlb_memoryCounts the number of Extended Page Table walks from the ITLB that hit in memoryAll retired load uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)All retired store uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Far branch instructions retiredl2_l1d_wb_rqsts.hit_mRetired load uops with L2 cache hits as data sources (Precise event)mem_load_uops_llc_miss_retired.local_dramL2 or LLC HW prefetches that access L2 cacheumask=0xa,period=100003,event=0xf2umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0091Counts all demand data writes (RFOs) that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x18000Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycleLoads with latency value being above 64 (Must be precise)offcore_response.demand_data_rd.llc_miss.dramFilter on cross-core snoops initiated by this Cbox due to external snoop requestUnit: uncore_arb Counts the number of allocated write entries, include full, partial, and LLC evictionsLLC lookup request that access cache and found line in E-state or S-stateumask=0x81,period=100003,event=0x8umask=0x88,period=100003,event=0x8offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwdCounts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedLLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_prefetch. Unit: uncore_cbox LLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x1c8llc_references.pcie_ns_writeCycles where receiving QPI link is in half-width mode. Unit: uncore_qpi unc_p_freq_ge_3000mhz_cyclesData from local DRAM either Snoop not needed or Snoop Miss (RspI)umask=0x8,period=2000003,event=0x51Cases of cancelling valid DSB fill not because of exceeding way limitagu_bypass_cancel.countumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000070offcore_response.partial_streaming_stores.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000402000offcore_response.partial_writes.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_request.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000020Counts any request that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_pf_l2.l2_hit_this_tile_foffcore_response.uc_code_reads.l2_hit_near_tileoffcore_response.partial_reads.l2_hit_far_tileCounts any Read request  that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800040Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Faroffcore_response.uc_code_reads.mcdramoffcore_response.any_data_rd.mcdramCounts Demand cacheable data writes that accounts for responses from DDR (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181802000Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far)umask=0x4,period=200003,event=0xcaCounts the number of occurences a retired load that is a cache line split. Each split should be counted only once  Supports address when precise (Precise event)Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is fullunc_m_cas_count.wrumask=0x2,period=100003,edge=1,event=0x5l1d_prefetch.triggersL1 writebacks to L2 in I state (misses)L2 lines alloacatedL2 lines evicted by a demand requestumask=0x2,period=100000,event=0xf2l2_rqsts.ifetch_hitl2_write.rfo.i_stateoffcore_requests.l1d_writebackMemory instructions retired above 32768 clocks (Precise Event)offcore_response.any_data.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF44umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8044Offcore requests satisfied by the LLC and HIT in a sibling coreoffcore_response.any_rfo.llc_hit_other_core_hitmOffcore RFO requests satisfied by the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1808umask=0x1,period=100000,event=0xb7,offcore_rsp=0x133Offcore demand code reads satisfied by the IO, CSR, MMIO unitoffcore_response.demand_ifetch.local_cacheOffcore demand RFO requests satisfied by any cache or DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3802Offcore prefetch code reads satisfied by any cache or DRAMoffcore_response.pf_ifetch.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8070umask=0x1,period=100000,event=0xb7,offcore_rsp=0x770Offcore requests satisfied by any DRAMOffcore requests satisfied by the local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6077Offcore request = all data, response = any LLC missoffcore_response.data_in.remote_dramOffcore data reads, RFO's and prefetches statisfied by the remote DRAMoffcore_response.pf_data_rd.any_dramumask=0x1,period=2000000,event=0xd5umask=0x4,period=20000,event=0x88Call branches executedInstruction Queue full stall cyclesRetired MMX instructions (Precise Event)MXCSR rename stall cyclesStack pointer sync operationsuops_executed.port5Retired stores that miss the DTLB (Precise Event)offcore_response.demand_data_rd.supplier_none.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080002period=2000003,umask=0x1,event=0x60period=200003,umask=0xe7,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080108000Counts demand data readshave any response typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801C0004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040001offcore_response.demand_rfo.l4_hit_local_l4.snoop_missfrontend_retired.latency_ge_8Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)Cycles with less than 3 uops delivered by the front-endperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x007C400004offcore_response.demand_rfo.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000001Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise (Must be precise)This event counts far branch instructions retired  Spec update: SKL091 (Precise event)cmask=16,period=2000003,umask=0x10,event=0xa3period=100003,umask=0x8,event=0x3Return instructions retired  Spec update: SKL091 (Precise event)inst_retired.any / mem_inst_retired.all_loadsInstructions per Store (lower number means higher occurrence rate)Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficStore uops that split cache line boundaryAny reissued store uopsumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000022umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680002000Counts DCU hardware prefetcher data read that miss L2 with a snoop miss responseCounts demand reads of partial cache lines (including UC and WC) that miss L2offcore_response.pf_l2_rfo.l2_miss.snoop_missCounts writeback (modified to exclusive) that miss L2umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000001NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksRetired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event)umask=0x2,period=100007,event=0xd4offcore_response.pf_l2_code_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400080umask=0x80,period=100000,event=0xb0offcore_requests.demand.read_codeumask=0x1,period=100000,event=0xb0umask=0x8,period=2000000,event=0x60offcore_requests_outstanding.demand.read_code_not_emptyumask=0x1,period=2000000,cmask=1,event=0x60umask=0x4,period=2000000,event=0x60REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIOREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIToffcore_response.any_ifetch.all_local_dram_and_remote_cache_hitREQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_DATA and RESPONSE = ANY_LOCATIONREQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5040REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMoffcore_response.any_ifetch.any_dram_and_remote_fwdREQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISSumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf833offcore_response.demand_data.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3080umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5801umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1850period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0122Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwdCounts all prefetch (that bring data to LLC only) RFOs that hit in the L3offcore_response.pf_l3_rfo.l3_hit.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000491Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dramoffcore_response.all_pf_data_rd.l3_miss.remote_hit_forwardCounts all prefetch data reads that miss the L3 and the data is returned from remote dramCounts all demand & prefetch RFOs that miss in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800122Counts all demand code reads that miss the L3 and the data is returned from remote dramCounts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.pf_l2_data_rd.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000080Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionsinst_retired.any / ( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )Rate of non silent evictions from the L2 cache per Kilo instructionMemoryLat;SoCcha_0@event\=0x0@Read Pending Queue Allocations. Unit: uncore_imc Counts the number of read requests allocated into the Read Pending Queue (RPQ).  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  The requests deallocate after the read CAS command has been issued to DRAM.  This event counts both Isochronous and non-Isochronous requests which were issued to the RPQPCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0. Unit: uncore_iio Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelinesLines Victimized; Lines in S State. Unit: uncore_cha fc_mask=0x04,umask=0x08,event=0xd5Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busWrite request of up to a 64 byte transaction is made to IIO Part2 by the CPU. Unit: uncore_iio Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU. Unit: uncore_iio unc_iio_txn_req_of_cpu.peer_read.part0unc_iio_txn_req_of_cpu.peer_read.part1Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part1Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socketMulti-socket cacheline Directory lookup (cacheline found in S state). Unit: uncore_m2m Reads to iMC issued at Normal Priority (Non-Isochronous). Unit: uncore_m2m Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, andIdle FLITs transmitted. Unit: uncore_upi ll period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_data_rd.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020490This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.all_reads.l3_hit.snoop_missoffcore_response.all_reads.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_reads.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200122offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200002offcore_response.demand_rfo.l3_hit_m.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0400offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_neededoffcore_response.pf_l3_data_rd.l3_hit_s.any_snoopoffcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080100( ( 64 * imc@event\=0xe3@ / 1000000000 ) / duration_time )ocr.all_data_rd.l3_miss.snoop_missOCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000120ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_neededocr.all_reads.l3_miss_local_dram.hitm_other_coreOCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000004ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000002Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.other.l3_miss_local_dram.no_snoop_neededCounts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_missocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000080ocr.pf_l3_data_rd.l3_miss.no_snoop_neededocr.pf_l3_data_rd.l3_miss.remote_hitmCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDOCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.supplier_none.no_snoop_neededOCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_COREOCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOPocr.all_pf_rfo.l3_hit_s.hit_other_core_fwdocr.all_pf_rfo.l3_hit_s.snoop_missOCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_s.any_snoopocr.all_reads.supplier_none.any_snoopOCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_COREOCR.ALL_RFO.L3_HIT_M.SNOOP_NONECounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.pmm_hit_local_pmm.any_snoopCounts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.demand_data_rd.l3_hit_m.any_snoopCounts any other requests  OCR.OTHER.L3_HIT_M.ANY_SNOOPCounts any other requests  OCR.OTHER.L3_HIT_S.ANY_SNOOPCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDEDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_s.snoop_missocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOPocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwdocr.pf_l2_rfo.l3_hit_s.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_m.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_neededocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_e.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDEDunc_m_pmm_rpq_inserts + unc_m_pmm_wpq_insertsumask=0x8,event=0xeaWrite commands for Intel Optane DC persistent memory. Unit: uncore_imc period=1000003,umask=0x82,event=0xd0period=100003,umask=0x1,event=0x2eDecode Stream Buffer (DSB)-to-MITE transitions countCounts retired Instructions who experienced Instruction L1 Cache true miss (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0004Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or notCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or notCounts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or notperiod=10000003,umask=0x1,event=0xa4Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataNumber of uops executed on port 1Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on addressCounts the number of machine clears (nukes) of any typeCounts cycles when at least 4 micro-ops are executed from any thread on physical corecmask=5,period=1000003,umask=0x5,event=0xa3cmask=1,inv=1,period=1000003,umask=0x1,event=0xeexe_activity.bound_on_loadsFor every cycle where the core is waiting on at least 1 outstanding demand RFO request, increments by 1.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor(cstate_core@c1\-residency@ / msr@tsc@) * 100Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event)2LM Tag Check : Miss, existing data may be evicted to Far Memory. Unit: uncore_imc umask=0x08,event=0xd3DRAM Clockticks. Unit: uncore_imc unc_cha_tor_occupancy.io_missunc_cha_tor_inserts.ia_rfoumask=0xCCC7FF01,event=0x35unc_cha_tor_occupancy.ia_miss_drd_remoteumask=0xC816FE01,event=0x35unc_cha_tor_inserts.io_hit_itomcachenearunc_cha_tor_inserts.io_hit_pcirdcurumask=0x1BC1FF,event=0x34Number Transactions requested of the CPU : Card writing to DRAM. Unit: uncore_iio fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0xc1fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0x84unc_iio_txn_req_of_cpu.mem_read.part6PCIe Completion Buffer Occupancy of completions with data : Part 2. Unit: uncore_iio Coherent Ops : WbMtoI. Unit: uncore_irp Clockticks of the mesh to PCI (M2P). Unit: uncore_m2pcie Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1Data requested of the CPU : Card writing to DRAM. Unit: uncore_iio period=200003,umask=0x41,event=0x2eCounts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM)period=200003,umask=0x82,event=0xd0period=200003,umask=0x2,event=0xcdbus_lock.cycles_other_blocktopdown_be_bound.non_mem_schedulerCounts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodesCounts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for (Precise event)period=200003,umask=0x80,event=0x8Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will results in a DTLB write from STLBThe number of instruction fetches that miss in both the L1 and L2 TLBsic_fetch_stall.ic_stall_anyThe number of ITLB reload requestsumask=0x40,event=0x64Retired Far Control TransfersRemote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0umask=0x02,event=0x807The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3Total number multi-pipe uOps assigned to pipe 2Total number of fp uOps  on pipe 0The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0umask=0x08,event=0x5fp_retired_ser_ops.sse_ctrl_retls_dispatch.ld_dispatchls_mab_alloc.dc_prefetcherls_l1_d_tlb_miss.tlb_reload_1g_l2_missumask=0x0c,event=0x46Total Page Table Walks IC Type 0ls_tablewalker.dc_type1100%l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3l2_cache_hits_from_ic_missesuops_dispatcheddata_fabricbp_l1_tlb_fetch_hit.if1gls_sw_pf_dc_fill.ls_mabresp_lcl_dramHardware Prefetch Data Cache Fills by Data Source. Local L2 hitThe number of times a branch used the indirect predictor to make a predictionThe number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size)umask=0xff,event=0x9aex_ret_fused_instrls_dmnd_fills_from_sys.ext_cache_remotede_dis_cops_from_decoder.disp_op_type.any_integer_dispatchCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stallde_dis_dispatch_token_stalls2.int_sch1_token_stallBU_INTERNAL_L2_REQUESTFR_RETIRED_FPU_INSTRUCTIONSFR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSFR_FPU_EXCEPTIONSFR_NUMBER_OF_BREAKPOINTS_FOR_DR1NB_HT_BUS0_BANDWIDTHEVENT_1FHEVENT_35HEVENT_6DHEVENT_A4HEVENT_B0HINSTR_RENAMEDDMB_STALLDATA_ENGINE_CLOCK_ENABLEDL1I_CACHEINST_SPECMEM_ACCESS_STSTREX_PASS_SPECDTLB_WALKMEM_BYTE_READTAGCACHE_WRITE_MISSBRANCH_COMPLETEDICACHE_ACCESSESOOO_ALU_ISSUE_CYCLESPREFETCH_INSNSTRAPVPU_INSTR_COMPLETEDL1_DATA_SNOOP_HIT_ON_MODIFIEDLSU_TOUCH_ALIAS_VS_CSQFP_ONE_QUARTER_FPSCR_RENAMES_BUSYFP_ALL_FPSCR_RENAMES_BUSYL1_DATA_TOUCH_MISS_CYCLESTLBSYNC_INSTR_COMPLETEDL2_CACHE_HITSL3_EXTERNAL_INTERVENTIONSTIMEBASE_EVENTDCACHE_MISS_COMPLETION_STALLstore-pipe-excluding-junk-opshslocked-instructionslow-op-pos-0probe-hit-dirty-no-memory-cancel+INTEL_ATOM_GOLDMONTINTEL_ICELAKE/usr/src/lib/libpmc/pmclog.cBRANCH_MISSES_RETIRED{"type": "proc_create"GenuineIntel-6-96C6_Pkg_ResidencyL2 prefetch requests that miss L2 cacheL2 prefetch requests that hit L2 cacheThis event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.
Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeumask=0x8,cmask=1,period=2000003,event=0x60umask=0x8,period=100003,event=0xb0offcore_requests_buffer.sq_fullmem_load_uops_retired.l1_missThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event)Demand Data Read requests that access L2 cacheother_assists.sse_to_avxNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementDeliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busyRTM region detected inside HLEhle_retired.abortedhle_retired.aborted_misc2cpl_cycles.ring123Instructions retired from executionThis event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
 - preceding store conflicts with the load (incomplete overlap);
 - store forwarding is impossible due to u-arch limitations;
 - preceding lock RMW operations are not forwarded;
 - store has the no-forward bit set (uncacheable/page-split/masked stores);
 - all-blocking stores are used (mostly, fences and port I/O);
and others.
The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.
See the table of not supported store forwards in the Optimization Guideumask=0xff,period=200003,event=0x88br_misp_exec.taken_return_nearumask=0x4,period=2000003,event=0xa2br_inst_retired.all_branches_pebsThis is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise)Uncore cache clock ticks. Unit: uncore_cbox All LLC Misses (code+ data rd + data wr - including demand and prefetch). Unit: uncore_cbox M line evictions from LLC (writebacks to memory). Unit: uncore_cbox llc_misses.uncacheableunc_h_snoop_resp.rspcnflctDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)  Spec update: BDM69umask=0x60,period=100003,event=0x49This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB cachesitlb_misses.walk_durationitlb.itlb_flushidq_uops_not_delivered.core / (4 * cycles)L1MPKIFraction of cycles where both hardware Logical Processors were activeumask=0x1,period=2000003,cmask=6,event=0x60Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)Counts all demand data writes (RFOs) have any response typeoffcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwdoffcore_response.pf_l3_data_rd.supplier_none.snoop_noneoffcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwdoffcore_response.pf_l3_data_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020200offcore_response.other.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0120offcore_response.all_data_rd.l3_hit.snoop_not_neededoffcore_response.all_data_rd.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010122Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementCounts randomly selected loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)offcore_response.corewb.l3_miss.snoop_missoffcore_response.pf_l2_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_noneoffcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitmoffcore_response.pf_l2_rfo.l3_miss.snoop_not_neededoffcore_response.pf_l2_rfo.l3_miss.snoop_missoffcore_response.pf_l3_data_rd.l3_miss.snoop_not_neededoffcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000100offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000240offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0091Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor coreUnit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor coreunc_cbo_cache_lookup.read_iumask=0x1f,event=0x34unc_cbo_cache_lookup.any_esumask=0x26,event=0x34offcore_response.all_requests.llc_miss.any_responseuncore_qpiumask=0x40,period=200000,event=0x26l2_m_lines_out.self.demandl2_ld.self.prefetch.e_statel2_ld.self.prefetch.m_stateumask=0x5f,period=200000,event=0x29umask=0x44,period=200000,event=0x2dl2_rqsts.self.any.s_stateumask=0x71,period=200000,event=0x30l2_reject_busq.self.prefetch.m_stateumask=0x52,period=200000,event=0x30l1d_cache.ldFloating point computational micro-ops executedumask=0x8,period=2000000,event=0xb3simd_uop_type_exec.logical.sumask=0x8,period=2000000,event=0xcaRetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsIcache missumask=0x2,period=2000000,event=0xaaumask=0x91,period=200000,event=0x5prefetch.sw_l2dispatch_blocked.anyNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsbus_lock_clocks.selfInvalidate bus transactionsumask=0xe0,period=200000,event=0x6aumask=0x40,period=200000,event=0x7dHardware interrupts receivedGood store forwardsumask=0x1,period=2000000,event=0x13All macro unconditional branch instructions, excluding calls and indirectsbr_missp_type_retired.condumask=0x1,period=200000,event=0xc3br_inst_retired.anyumask=0x21,period=200003,event=0xd0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x02000032b7Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.hitm_other_coreoffcore_response.any_request.any_responseCounts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000800offcore_response.pf_l2_data_rd.l2_hitCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.outstandingCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitectureumask=0x3,period=200003,event=0x80misalign_mem_ref.store_page_splitCounts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise)ld_blocks.all_blockInteger divide uops retired. (Precise Event Capable) (Must be precise)Counts BACLEARS on return instructionsCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor moduleCounts bus lock and split lock requests have any transaction responses from the uncore subsystemCounts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor moduleumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000001000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010022umask=0x0,period=2000003,event=0xc0umask=0x20,period=20003,event=0xc3Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages.  The page walks can end with or without a page faultumask=0x2,period=2000003,event=0x49umask=0x4,period=2000003,event=0x49Page walks outstanding due to a demand data store every cycleData read requests sent to uncore (demand and prefetch)Retired store uops that miss the STLB. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performanceThis event counts Instruction Cache (ICACHE) misseshsw metricsNumber of times a transactional abort was signaled due to a data capacity limitation for transactional writesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x01004007F7offcore_response.pf_l3_code_rd.l3_miss.any_responseCycles which a uop is dispatched on port 6 in this threadResource-related stall cycles  Spec update: HSD135Mispredicted macro branch instructions retired (Must be precise)umask=0x41,event=0x34DTLB demand load misses with low part of linear-to-physical address translation missedCounts the number of Extended Page Table walks from the DTLB that hit in the L2Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: HSM30 (Precise event)offcore_response.pf_llc_data_rd.llc_hit.any_responseNumber of X87 FP assists due to output valuesumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400244Retired load uops which data sources were data hits in LLC without snoops required (Precise event)mem_load_uops_llc_hit_retired.xsnp_noneoffcore_response.all_data_rd.llc_hit.any_responseCounts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0002Loads with latency value being above 32 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400091offcore_response.all_reads.llc_miss.dramCounts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0unc_cbo_xsnp_response.external_filterunc_cbo_cache_lookup.eCounts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLCCounts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c03f7offcore_response.other.lru_hintsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0010Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts demand data reads that miss in the LLCoffcore_response.pf_l2_data_rd.llc_miss.local_dramPCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit. Unit: uncore_cbox PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write. Unit: uncore_cbox Occupancy for all LLC misses that are addressed to remote memory. Unit: uncore_cbox (unc_q_rxl0p_power_cycles / unc_q_clockticks) * 100.Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified stateRetired load uops which data sources were HitM responses from shared LLCThis event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlierThis event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructionsRetired instructions experiencing ITLB missesEach cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDINGumask=0xc,period=2000003,event=0x5bresource_stalls2.ooo_rsrcCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu l2_requests.missThis event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be countedCounts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400022Counts Demand cacheable data write requests  that accounts for any responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400004offcore_response.demand_data_rd.l2_hit_far_tile_mCounts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.partial_reads.l2_hit_this_tile_eCounts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000400offcore_response.any_code_rd.l2_hit_this_tile_sCounts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F stateCounts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800188000Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_rfo.l2_hit_far_tileoffcore_response.any_code_rd.l2_hit_far_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800070Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00808032f7umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080202000Counts Software Prefetches that accounts for data responses from DRAM Farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400400offcore_response.partial_writes.mcdram_nearoffcore_response.pf_l2_code_rd.mcdram_faroffcore_response.pf_l2_rfo.ddr_faroffcore_response.demand_rfo.ddrumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181801000offcore_response.any_rfo.ddrCounts the number of branch instructions retired that were conditional jumps (Precise event)umask=0x90,period=200003,event=0xcars_full_stall.mecrs_full_stall.allCycles the number of core cycles when divider is busy.  Does not imply a stall waiting for the dividerl1d_cache_lock.e_stateumask=0x2,period=100000,event=0x28l2_transactions.ifetchL2 Load transactionsL2 prefetch transactionsL2 demand lock RFOs in S stateLoad instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)umask=0x1,period=100000,event=0xb2Offcore requests blocked due to Super Queue fullmem_inst_retired.latency_above_threshold_0mem_inst_retired.latency_above_threshold_16Memory instructions retired above 16 clocks (Precise Event)mem_inst_retired.latency_above_threshold_8192offcore_response.any_ifetch.llc_hit_other_core_hitoffcore_response.any_ifetch.remote_cache_hitmoffcore_response.any_rfo.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1822All offcore writebacksumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8008umask=0x1,period=100000,event=0xb7,offcore_rsp=0x408Offcore code or data read requests satisfied by the IO, CSR, MMIO unitoffcore_response.data_ifetch.local_cacheOffcore request = all data, response = remote cache or dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x401Offcore demand code reads that HITM in a remote cacheoffcore_response.demand_rfo.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x202offcore_response.other.remote_cache_hitoffcore_response.pf_data_rd.io_csr_mmioumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1810Offcore prefetch data reads that HITM in a remote cacheumask=0x80,period=2000000,event=0x10SSE FP packed UopsOffcore data reads satisfied by any DRAMoffcore_response.data_ifetch.remote_dramoffcore_response.demand_data_rd.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6001umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2001Offcore demand RFO requests satisfied by the local DRAMLoads dispatched from the MOBpartial_address_aliassnoop_response.hiteumask=0x7,period=200000,event=0x88br_inst_exec.takenbr_misp_exec.indirect_near_callCycles no uops were delivered by the LSDresource_stalls.fpcwoffcore_response.demand_data_rd.l3_hit_e.any_snoopperiod=200003,umask=0x40,event=0xf0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200028000period=2000003,umask=0x4,event=0x60period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040002offcore_response.other.l3_hit_e.snoop_hit_no_fwdperiod=2000003,umask=0x1,event=0x51Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00401C8000offcore_response.other.l3_hit_m.snoop_hit_no_fwdperiod=2000003,umask=0x4,event=0x80Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event)Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQCounts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cyclesCounts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000080004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C400001period=2000003,umask=0x1,event=0x54period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000001period=2000003,umask=0x20,event=0xc9Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)exe_activity.4_ports_utilperiod=2000003,umask=0x10,event=0xb1period=2000003,umask=0x8,event=0xa6Taken branch instructions retired  Spec update: SKL091 (Precise event)period=100007,umask=0x2,event=0xc4period=100003,umask=0x4,event=0xc3period=2000003,umask=0x1,event=0xa6uops_issued.vector_width_mismatchperiod=2000003,umask=0x1,event=0x5eThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU( uops_issued.any - uops_retired.retire_slots + 4 * ( int_misc.recovery_cycles_any / 2 ) ) / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * ( int_misc.recovery_cycles_any / 2 ) ) / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) ) * (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) / br_misp_retired.all_branchesperiod=100003,umask=0xe,event=0x85Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultCounts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultCounts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other eventsrehabq.lockCounts any code reads (demand & prefetch) that miss L2 with a snoop miss responseCounts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedRETURN counts the number of near RET branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)This event counts the number of load uops retired (Precise Event) (Precise event)Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event)Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCounts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2380408000offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10080offcore_response.all_pf_code_rd.llc_miss.dramThis event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAMumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80408fffREQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DATA_IN and RESPONSE = LOCAL_CACHEoffcore_response.demand_ifetch.all_local_dram_and_remote_cache_hitoffcore_response.pf_ifetch.local_dram_and_remote_cache_hitoffcore_response.any_data.any_dram_and_remote_fwdoffcore_response.any_ifetch.other_local_dramREQUEST = ANY RFO and RESPONSE = REMOTE_DRAMoffcore_response.pf_ifetch.other_local_dramload_block.overlap_storesnoopq_requests_outstanding.datasnoopq_requests_outstanding.data_not_emptyumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5820Retired load instructions which data sources missed L3 but serviced from remote dram  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0004OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0100Counts all prefetch data reads that miss in the L3offcore_response.all_pf_rfo.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000120Flops_SMTFlops;HPCunc_m_cas_count.rd_regRead Pending Queue Occupancy. Unit: uncore_imc write requests from local home agent. Unit: uncore_cha Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s)Multi-socket cacheline Directory state lookups; Snoop Not Needed. Unit: uncore_cha Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe. Unit: uncore_cha Read request from a remote socket which hit in the HitMe Cache to a line In the E state. Unit: uncore_cha Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHACounts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelinePCIe Completion Buffer Inserts of completions with data: Part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_write.part0uncore_m2mCycles when direct to core mode (which bypasses the CHA) was disabled. Unit: uncore_m2m Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overriddenReads to iMC issued. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priority. Unit: uncore_m2m Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHAumask=0x97,event=0x3Valid Flits Sent; Data. Unit: uncore_upi ll period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080491offcore_response.all_data_rd.l3_hit_e.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C07F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000407F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08001007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000207F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000207F7This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.all_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.other.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0010offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040010offcore_response.pf_l2_rfo.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400020offcore_response.pf_l3_data_rd.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORENumber of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementocr.all_data_rd.l3_miss.hit_other_core_fwdocr.all_data_rd.l3_miss.snoop_noneocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOPocr.all_pf_rfo.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000120OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss.hitm_other_coreocr.all_reads.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000122ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_coreOCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITMocr.demand_code_rd.l3_miss.snoop_missCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_missCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000002ocr.demand_rfo.l3_miss_local_dram.hitm_other_coreCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000020ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000100offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.all_pf_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.other.l3_miss.hitm_other_coreoffcore_response.other.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDOCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDOCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONEOCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOPOCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwdocr.all_pf_rfo.l3_hit_e.hitm_other_coreOCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOPOCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOPocr.all_rfo.pmm_hit_local_pmm.any_snoopocr.demand_code_rd.any_responseocr.demand_code_rd.l3_hit.hit_other_core_no_fwdocr.demand_code_rd.l3_hit.snoop_hit_with_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORECounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.demand_data_rd.any_responseCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_f.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDEDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORECounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOPCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.other.l3_hit_e.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests have any response typeocr.pf_l1d_and_sw.l3_hit_f.snoop_missCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWDCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwdocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwdocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_s.snoop_noneocr.pf_l2_rfo.l3_hit.hit_other_core_fwdocr.pf_l2_rfo.l3_hit_f.snoop_noneocr.pf_l2_rfo.supplier_none.hit_other_core_fwdocr.pf_l3_rfo.l3_hit_e.snoop_missocr.pf_l3_rfo.l3_hit_f.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwdocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDunc_m_pmm_bandwidth.totalAll commands for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_tagchk.hitUops delivered to IDQ while MS is busyperiod=100003,umask=0x80,event=0xc8Number of times an RTM execution abortedCounts the number of times RTM abort was triggeredocr.other.l3_hit.snoop_not_neededCounts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the requestCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sentocr.demand_data_rd.l3_hit.snoop_hit_no_fwdNumber of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3)ocr.hwpf_l2_rfo.l3_hit.snoop_missbr_inst_retired.indirectcmask=1,period=1000003,umask=0x9,event=0x14Cycles without actually retired instructionsCounts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event)period=100003,umask=0x40,event=0xccperiod=2000003,umask=0x8,event=0x3cumask=0x0f,event=0x4All DRAM CAS commands issued. Unit: uncore_imc TOR Inserts : All requests from iA Cores that Hit the LLC. Unit: uncore_cha TOR Inserts : ItoMs issued by IO Devices that missed the LLC. Unit: uncore_cha TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_llcprefrfoTOR Inserts : LLCPrefRFO issued by iA Cores. Unit: uncore_cha umask=0xC8C7FF01,event=0x35unc_cha_tor_inserts.ia_miss_full_streaming_wrTOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.io_miss_pcirdcurunc_iio_data_req_of_cpu.mem_read.part4fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0xc1unc_iio_txn_req_of_cpu.mem_write.part7unc_m2m_clockticksClockticks of the power control unit (PCU). Unit: uncore_pcu umask=0xC001FE01,event=0x35,config1=0x41833mem_bound_stalls.load_llc_hitbaclears.indirectCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cachetopdown_be_bound.serializationtopdown_retiring.allCounts the total number of consumed retirement slots (Precise event)cpu_clk_unhalted.ref_tsc_pCounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervalsl2_request_g2.ls_rd_sized_ncl2_cache_req_stat.ls_rd_blk_l_hit_xuncore_l3pmcThe number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instructionfpu_pipe_assignment.dual1The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3fpu_pipe_assignment.total1umask=0x08,event=0x3fp_ret_sse_avx_ops.sp_add_sub_flopsumask=0x08,event=0x45event=0x76ic_oc_mode_switch.ic_oc_mode_switchumask=0x20,event=0xafumask=0xc8,event=0x60l2_cache_accesses_from_l2_hwpfevent=0xd2Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reasonCycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP opsde_dis_dispatch_token_stalls1.store_queue_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination registerop_cache_hit_miss.all_op_cache_accessesop_cache_hit_miss.op_cache_missls_dmnd_fills_from_sys.int_cacheL1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLBls_misal_loads.ma4kSoftware Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevelumask=0x04,event=0x59Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Nodels_hw_pf_dc_fills.lcl_l2ls_alloc_mab_countls_tlb_flush.all_tlb_flushesL1 Data Cache Fills: From within same CCXEVENT_21HEVENT_25HEVENT_4CHEVENT_ABHEVENT_BDHEVENT_F2HSECOND_EXECUTION_UNIT_PIPEWRITE_STALLBUS_ACCESS_LDST_RETIREDPC_WRITE_RETIREDUNALIGNED_LDST_RETIREDL1D_TLB_REFILL_LDL2D_CACHE_STREMOTE_ACCESSICACHE_WRITE_HITDCACHE_SET_TAG_WRITEMEM_HWORD_READMEM_HWORD_WRITETAGCACHEMASTER_WRITE_REQ_FLITTAGCACHEMASTER_READ_RSP_FLITFPU_STALL_CYCLESLOAD_TO_USE_STALLSALU_OPERANDS_NOT_READY_CYCLESJTLB_DATA_ACCESSESFSB_OVER_50_FULLLOAD_MISS_INSNSSYSTEM_EVENT_3OCP_WRITE_REQUESTSULOADSTSIOSTSVIU1_INSTR_WAIT_CYCLESSUCCESSFUL_DST_TABLE_SEARCHESL2_EXTERNAL_INTERVENTIONSL2_LOAD_MISSGUARDED_LOADS_TRANSLATEDDATA_L1_CACHE_RELOADSDVT3_DETECTEDaccessesnonpostwrszdwordrdszbyteINTEL_PMINTEL_SKYLAKEUNHALTED-CORE-CYCLESex_ret_brn_mispCPU_CLK_UNHALTED.THREAD_P_ANYBR_INST_RETIRED.ALL_BRANCHESldlatv18GenuineIntel-6-55-[56789ABCDEF]l1d_pend_miss.pending / ( mem_load_uops_retired.l1_miss + mem_load_uops_retired.hit_lfb )Memory_Bound;Memory_LatSMT;Summarylongest_lat_cache.missumask=0x41,period=100003,event=0x2eumask=0x1,cmask=6,period=2000003,event=0x60Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76offcore_requests_outstanding.demand_rfoRetired load uops that split across a cacheline boundary.(Precise Event - PEBS)  Supports address when precise (Precise event)This event counts L2 or L3 HW prefetches that access L2 cache including rejectsidq.dsb_uopsCycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathhle_retired.startNumber of times HLE caused a faultNumber of intervals between processor halts while thread is in ring 0Core cycles when the thread is not in halt stateload_hit_pre.sw_pfTaken speculative and retired indirect branches excluding calls and returnsbr_inst_exec.taken_indirect_near_returnThis event counts both taken and not taken speculative and retired direct near callsbr_misp_exec.nontaken_conditionalumask=0xa0,period=200003,event=0x89This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4uops_dispatched_port.port_6resource_stalls.robcycle_activity.cycles_ldm_pendingNumber of uops executed from any threadinst_retired.x87This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handlingMispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise)llc_misses.pcie_readumask=0x2,event=0x1power_critical_throttle_cycles %Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. Unit: uncore_pcu itlb_misses.stlb_hitpage_walker_loads.dtlb_l3Number of DTLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98TopdownL1_SMTThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core BoundThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPUmin( 1 , idq.mite_uops / ( (uops_retired.retire_slots / inst_retired.any) * 16 * ( icache.hit + icache.misses ) / 4.0 ) )L1D_Cache_Fill_BWThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache  Spec update: BDM35.  Supports address when precise (Precise event)Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020001Counts all demand data writes (RFOs)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020004offcore_response.demand_code_rd.l3_hit.snoop_hitmoffcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwdoffcore_response.pf_l2_code_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020040offcore_response.pf_l3_code_rd.l3_hit.snoop_noneoffcore_response.pf_l3_code_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000018000offcore_response.all_pf_rfo.supplier_none.snoop_missoffcore_response.all_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020122umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0122This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable  Spec update: BDM30umask=0x8,period=2000003,cmask=1,event=0x79offcore_response.demand_data_rd.l3_miss_local_dram.snoop_noneoffcore_response.demand_rfo.l3_miss.snoop_not_neededoffcore_response.demand_code_rd.l3_hit.snoop_non_dramoffcore_response.demand_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0008offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000080offcore_response.pf_l3_rfo.supplier_none.snoop_non_dramoffcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dramoffcore_response.other.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000240offcore_response.all_rfo.l3_miss_local_dram.snoop_noneL3 Lookup read request that access cache and found line in any MESI-stateunc_arb_trk_requests.writesThis 48-bit fixed counter counts the UCLK cyclesThis event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)offcore_response.all_rfo.llc_hit.hit_other_core_no_fwdNumber of times HLE abort was triggered (Precise event)offcore_response.all_rfo.llc_miss.local_dramThis event counts return instructions retired (Precise event)l2_ld.self.prefetch.i_statel2_lock.self.m_statel2_rqsts.self.any.m_statel2_reject_busq.self.any.e_statex87_comp_ops_exe.fxch.arumask=0x81,period=10000,event=0x11umask=0x82,period=2000000,event=0xb3SIMD packed arithmetic micro-ops retiredumask=0x2,period=2000000,event=0xcaumask=0x1,period=2000000,event=0x86Cycles during which instruction fetches are  stalledumask=0x1,period=2000000,event=0x87Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedumask=0xf,period=200000,event=0x7Bus cycles when data is sent on the busbus_trans_wb.all_agentsumask=0x40,period=200000,event=0x6dhw_int_rcvumask=0x1,period=200000,event=0x89uops_retired.stallsumask=0x8,period=200000,event=0xc4umask=0x2,period=200000,event=0x82umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043091Counts data reads generated by L1 or L2 prefetchers that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_neededCycles code-fetch stalled due to an outstanding ITLB missumask=0x2,period=200003,event=0xcdumask=0x1,period=200003,event=0x5ITLB missesumask=0x12,period=200003,event=0xd0mem_uops_retired.dtlb_missCounts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystemoffcore_response.pf_l1_data_rd.outstandingCounts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page faultCounts all L2 HW prefetcher requests that hit L2l1d_pend_miss.request_fb_fullThis event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event  Spec update: HSM30.  Supports address when precise (Precise event)Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed addressoffcore_response.all_code_rd.l3_miss.local_dramoffcore_response.all_data_rd.l3_miss.any_responseThe number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useReference cycles when the thread is unhalted. (counts at 100 MHz rate)umask=0x8,period=100003,event=0xc4Counts all not taken macro branch instructions retired (Precise event)Count cases of saving new LBR records by hardwareunc_cbo_cache_lookup.extsnp_esITLB misses that hit STLB (4K)umask=0x1,period=100003,event=0xaeNumber of ITLB page walker hits in the L3 + XSNP  Spec update: HSD25Cycles with any input/output SSE* or FP assistsNumber of far branches retiredl2_rqsts.pf_missoffcore_response.all_code_rd.llc_hit.any_responseCounts all writebacks from the core to the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0001offcore_response.demand_data_rd.llc_hit.no_snoop_neededCount issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stallCounts all demand & prefetch code reads that miss the LLC  and the data returned from dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004001b3Cycles per core when load or STA uops are dispatched to port 3Counts total number of uops to be executed per-core each cycleA snoop misses in some processor coreunc_cbo_cache_lookup.read_filterUnit: uncore_arb Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLCunc_arb_trk_requests.evictionsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0001PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write. Unit: uncore_cbox Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Counts the number of times that the uncore transitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Retired load uops which data sources were hits in LLC without snoops requiredEach cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDINGtor_occupancy.miss_all %offcore_response.any_code_rd.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080200umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080100Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_rfo.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000002Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_data_rd.l2_hit_this_tile_soffcore_response.uc_code_reads.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000001umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000040Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_rfo.l2_hit_this_tile_fCounts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l1_data_rd.l2_hit_near_tileoffcore_response.any_request.l2_hit_near_tileCounts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_read.mcdram_faroffcore_response.pf_software.mcdram_nearCounts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200100Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180601000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01806032f7umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800022Counts the number of micro-ops retiredumask=0x20,period=200003,event=0xcaumask=0x7f,period=200003,event=0xcaFixed Counter: Counts the number of unhalted reference clock cyclesCounts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be countedThis event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progressumask=0x2,period=2000000,event=0x51L1 data cache lines allocatedL1 data cache read in E stateL1 data cache read in I state (misses)umask=0x8,period=2000000,event=0x42l1d_cache_prefetch_lock_fb_hitumask=0xf0,period=200000,event=0x26L2 demand lock RFOs in M stateumask=0x10,period=20000,event=0xb,ldlat=0x8offcore_response.any_request.io_csr_mmioOffcore requests satisfied by the LLCOffcore requests satisfied by a remote cache or remote DRAMOffcore requests that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x122umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1022umask=0x1,period=100000,event=0xb7,offcore_rsp=0x708Offcore writebacks to the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4708offcore_response.data_ifetch.any_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3877offcore_response.data_in.llc_hit_no_other_coreOffcore demand data requests satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F01offcore_response.demand_ifetch.remote_cache_dramoffcore_response.other.llc_hit_other_core_hitmOffcore other requests satisfied by a remote cache or remote DRAMoffcore_response.pf_data_rd.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x810offcore_response.pf_ifetch.any_locationoffcore_response.pf_ifetch.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1820fp_mmx_trans.to_mmxumask=0x8,period=200000,event=0x12offcore_response.any_data.local_dramOffcore demand data requests that missed the LLCOffcore demand RFO requests that missed the LLCoffcore_response.other.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2030umask=0x2,period=2000000,event=0x80umask=0x1,period=100000,event=0x3cCycles when thread is not halted (fixed counter)umask=0x8,period=2000000,event=0x87umask=0x2,period=2000000,event=0xc0Loops that can't stream from the instruction queueinv=1,umask=0x3f,any=1,period=2000000,cmask=1,edge=1,event=0xb1inv=1,umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1Cycles no Uops issued on ports 0, 1 or 5Uops executed on port 1uops_issued.fusedRetirement slots used (Precise Event)itlb_miss_retiredITLB miss page walksoffcore_response.demand_data_rd.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001C0004period=2000003,umask=0x82,event=0xd0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040001offcore_response.demand_data_rd.l3_hit_s.snoop_missperiod=200003,umask=0xe4,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040080002offcore_response.demand_rfo.l3_hit_s.spl_hitCore-originated cacheable demand requests that refer to L3  Spec update: SKL057period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000400004period=100007,umask=0x4,event=0xd4period=200003,umask=0xd8,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040400001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040002period=100007,umask=0x1,event=0xc6,frontend=0x410006period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000020002period=2000003,umask=0x8,event=0x54period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000100001offcore_response.other.l3_hit_m.snoop_non_dramoffcore_response.other.l3_miss_local_dram.spl_hitoffcore_response.demand_rfo.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000400001offcore_response.demand_code_rd.l3_miss_local_dram.spl_hitNumber of PREFETCHT0 instructions executedNumber of PREFETCHT1 or PREFETCHT2 instructions executedCounts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructionsPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: SKL091, SKL044 (Must be precise)Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assistsrob_misc_events.pause_instIpBranchInstructions per (near) call (lower number means higher occurrence rate)Page walk completed due to a demand data store to a 2M/4M pageperiod=100003,umask=0x10,event=0x85period=2000003,umask=0x8,event=0x8rehabq.ld_splitsThis event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be countedThis event counts the number of load ops retired that had UTLB missCounts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cacheoffcore_response.corewb.l2_miss.no_snoop_neededCounts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts the number of cycles when no uops are allocated and a RATstall is assertedCounts the number of baclearsThis event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event)Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.demand_rfo.llc_hit_m.hitmREQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITMREQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = OTHER and RESPONSE = IO_CSR_MMIOREQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1050REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITMREQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf877umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf804umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf802umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3070umask=0x80,period=200000,event=0x49umask=0x4,period=2000000,event=0x85umask=0x1,period=100000,event=0xb7,offcore_rsp=0x27FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2780Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise (Precise event)offcore_response.all_pf_rfo.l3_miss.remote_hit_forwardoffcore_response.all_rfo.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00001Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dramoffcore_response.pf_l3_rfo.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800100( ( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single ) / 1000000000 ) / duration_time1000000000 * ( cha@event\=0x36\,umask\=0x21\,config\=0x40433@ / cha@event\=0x35\,umask\=0x21\,config\=0x40433@ ) / ( cha_0@event\=0x0@ / duration_time )MEM_Read_Latencyunc_cha_requests.reads_localread requests from remote home agent. Unit: uncore_cha FaST wire asserted; Horizontal. Unit: uncore_cha Rsp*WB Snoop Responses Received. Unit: uncore_cha unc_iio_comp_buf_inserts.cmpd.part3unc_iio_comp_buf_occupancy.cmpd.part1fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc0Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part2Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part0unc_i_coherent_ops.pcitomevent=0x26Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)unc_m2m_directory_update.a2iumask=0x1,event=0x2ePartial Non-Isochronous writes to the iMC. Unit: uncore_m2m unc_m2m_prefcam_demand_promotionsAD Egress (to CMS) Allocations. Unit: uncore_m2m Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghzunc_upi_txl0p_power_cyclesunc_upi_txl_flits.dataThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_data_rd.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwdoffcore_response.all_pf_rfo.l3_hit_e.snoop_missoffcore_response.all_pf_rfo.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F804007F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020004offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISSoffcore_response.demand_rfo.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040400offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_coreoffcore_response.pf_l1d_and_sw.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l1d_and_sw.supplier_none.any_snoopoffcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400080This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000120OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F840007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000122OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARDOCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_code_rd.l3_miss_local_dram.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.demand_data_rd.l3_miss.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000001ocr.demand_data_rd.l3_miss.snoop_missCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.other.l3_miss.hit_other_core_no_fwdCounts any other requests OCR.OTHER.L3_MISS.SNOOP_MISSocr.other.l3_miss.snoop_noneocr.other.l3_miss_local_dram.hit_other_core_fwdocr.other.l3_miss_local_dram.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_missocr.pf_l2_rfo.l3_miss.remote_hitmocr.pf_l2_rfo.l3_miss.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000020ocr.pf_l3_data_rd.l3_miss.snoop_noneCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000080ocr.pf_l3_rfo.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONEocr.all_data_rd.supplier_none.snoop_noneOCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOPocr.all_pf_data_rd.l3_hit_f.hitm_other_coreocr.all_pf_data_rd.l3_hit_m.snoop_noneocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwdocr.all_pf_rfo.l3_hit.hitm_other_coreOCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDOCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONEOCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISSOCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWDOCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_s.hit_other_core_no_fwdOCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWDCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOPCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORECounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_f.hitm_other_coreocr.other.supplier_none.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWDCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.supplier_none.snoop_missocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwdocr.pf_l2_data_rd.l3_hit_s.hitm_other_coreCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwdocr.pf_l2_rfo.l3_hit_s.any_snoopCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOPCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_e.no_snoop_neededocr.pf_l3_rfo.l3_hit_f.any_snoopocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwdocr.pf_l3_rfo.l3_hit_m.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDAll commands for Intel Optane DC persistent memoryUnderfill read commands for Intel Optane DC persistent memory. Unit: uncore_imc Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path1000 * ( ( offcore_requests.all_data_rd - offcore_requests.demand_data_rd ) + l2_rqsts.all_demand_miss + l2_rqsts.swpf_miss ) / inst_retired.anyCounts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock BufferNumber of times an instruction execution caused the transactional nest count supported to be exceededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00400Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sentperiod=100003,umask=0x7,event=0xc1Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)cmask=16,period=1000003,umask=0x10,event=0xa3Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operationsCounts taken conditional branch instructions retired (Precise event)Counts end of periods where the Reservation Station (RS) was emptyperiod=400009,umask=0x11,event=0xc4cmask=5,period=2000003,umask=0x1,event=0xa8Counts all requests that miss L2 cachetgl metricsThis event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD  Supports address when precise (Precise event)unc_m_rpq_inserts.pch0unc_m_rpq_inserts.pch1unc_m_wpq_inserts.pch0DRAM Precharge commands. Unit: uncore_imc umask=0x01,event=0xeaTOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC. Unit: uncore_cha umask=0xC887FF01,event=0x35unc_cha_tor_occupancy.ia_drdunc_cha_tor_occupancy.ia_miss_drd_localunc_cha_tor_inserts.ia_miss_drd_localumask=0xC8178A01,event=0x36TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha TOR Inserts : PCIRdCurs issued by IO Devices. Unit: uncore_cha fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0x83fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0x83fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0xc1fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0x84fc_mask=0x04,ch_mask=0x08,umask=0x03,event=0xc2PCIe Completion Buffer Inserts of completions with data: Part 0-7. Unit: uncore_iio CMS Clockticks. Unit: uncore_m2m Cycles in L1. Unit: uncore_upi ll Valid Flits Sent : Null FLITs transmitted to any slot. Unit: uncore_upi ll Valid Flits Received : Null FLITs received from any slot. Unit: uncore_upi ll Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM)period=200003,umask=0x80,event=0xd1Counts the number of load uops retired that hit in the L2 cache  Supports address when precise (Precise event)period=200003,umask=0x81,event=0xd0ehl metricsbaclears.uncondCounts the number of instruction cache missesperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001period=1000003,umask=0x6,event=0x73Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event)period=2000003,umask=0x1,event=0x3cCounts the number of cycles the integer divider is busy.  Does not imply a stall waiting for the dividerevent=0x8aic_fetch_stall.ic_stall_dq_emptyl2_request_g1.ls_rd_blk_c_sl2_request_g2.bus_locks_originatorumask=0x01,event=0x63LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requestsL3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc event=0xc9Retired Near Returns Mispredictedevent=0xd1umask=0x38,event=0x7The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipesThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimizedThe number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bitsfp_retired_ser_ops.x87_bot_retumask=0x40,event=0x45de_dis_dispatch_token_stalls0.alsq2_token_stallAll L2 Cache Accessesl2_cacheL2 Cache Accesses from L2 HWPFThe number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB pagebp_l1_tlb_miss_l2_tlb_missfp_ret_sse_avx_ops.div_flopsumask=0x10,event=0x59umask=0x08,event=0x5aHardware Prefetch Data Cache Fills by Data Source. From another cache (home node local)Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP schedulerThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K pageThe number of retired branch instructions, that were mispredictedls_mab_alloc.all_allocationsumask=0x40,event=0x41Any Data Cache Fills by Data Source. From DRAM or IO connected in same nodeL1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLBde_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrcL3 Misses (includes cacheline state change requests). Unit: uncore_l3pmc Op Cache (64B) Fetch Miss RatiodecoderCPU_CLK_UNHALTED_COREFR_TAKEN_HARDWARE_INTERRUPTSCID_WRITEEVENT_15HEVENT_28HEVENT_2BHEVENT_9CHEVENT_CDHFLOATING_POINT_INSTR_RENAMEDEXC_TRAP_IRQTAGCACHE_EVICTSTORE_MISSSTORE_COND_FAILEDALU_CYCLES_STALLEDL2_MISS_CYCLESCOREXTEND_STALL_CYCLESIFETCH_BUFFER_FULLJR_31_NO_PREDICTIONSL2_CACHE_MISSESCACHE_HIT_PREFETCH_INSNSSYSTEM_EVENT_0MCFPU_RENORMALIZATIONLD_ST_TRUE_ALIAS_STALLLWARX_INSTR_COMPLETEDL1_DATA_TOUCH_MISSL3SQ_FULL_CYCLESFXU0_BUSY_FXU1_BUSYLSU_MARKED_INSTR_FINISHWRITE_THROUGH_STORES_TRANSLATEDCRIT_INPUT_INTR_TAKENL2_HIT_CACHE_ACCESSESFPU_FINISHLOAD_RETRIESTSC-osstoredram-controller-interface-bypassP4MIPS_74KPPC_E500GENERICARMV7_CORTEX_A17BRANCH_INSTRUCTION_RETIREDinst_retired.any_p{"type": "procexit"BAClear_CostMemory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)cpu_clk_unhalted.ref_tsc / msr@tsc@(cstate_core@c3\-residency@ / msr@tsc@) * 100l2_rqsts.code_rd_missl2_rqsts.all_rfoumask=0xe7,period=200003,event=0x24Core-originated cacheable demand requests missed L3L1D miss oustandings duration in cyclesCycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76umask=0x2,period=100003,event=0xb0umask=0x81,period=2000003,event=0xd0All retired load uops. (Precise Event - PEBS)  Supports address when precise (Precise event)This event counts L2 fill requests that access L2 cacheumask=0x4,period=100003,event=0xf1Clean L2 cache lines evicted by demandThis event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable  Spec update: BDM30Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementThis event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetchesumask=0x2,period=2000003,event=0x5drtm_retired.aborteduops_issued.flags_mergeedge=1,inv=1,umask=0x1,cmask=1,period=200003,event=0x5eumask=0x81,period=200003,event=0x88Speculative and retired indirect return branchesbr_inst_exec.all_direct_near_callThis event counts taken speculative and retired mispredicted macro conditional branch instructionsuops_dispatched_port.port_0uops_executed_port.port_0Cycles per core when uops are dispatched to port 7This event increments by 1 for every cycle where there was no execute for this threadExecution stalls while L1 cache miss demand load is outstandingmachine_clears.countumask=0x1,period=400009,event=0xc4Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event)umask=0x4,period=400009,event=0xc5umask=0x3,event=0x35,filter_opc=0x191ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.streaming_fullStreaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x2,event=0x21unc_p_power_state_occupancy.cores_c3unc_p_freq_max_power_cyclesdtlb_load_misses.miss_causes_a_walkumask=0x8,period=2000003,event=0x8Store misses in all DTLB levels that cause completed page walks  Spec update: BDM69umask=0x2,period=100003,event=0x85Store miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69umask=0x24,period=2000003,event=0xbcDTLB flush attempts of the thread-specific entriesThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoidedSLOTS_SMTL3 cache true misses per kilo instruction for retired demand loadsumask=0x1,any=1,period=2000003,cmask=1,event=0x48umask=0x8,period=2000003,cmask=1,event=0x60This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Spec update: BDM100.  Supports address when precise (Precise event)offcore_response.demand_data_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0020Counts all prefetch (that bring data to LLC only) code readsoffcore_response.pf_l3_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0080offcore_response.pf_l3_rfo.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400028000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020120offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwdoffcore_response.all_pf_rfo.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020120offcore_response.all_pf_rfo.l3_hit.snoop_missoffcore_response.all_pf_code_rd.l3_hit.snoop_not_neededCounts all demand & prefetch data reads have any response typeoffcore_response.all_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0122offcore_response.demand_code_rd.l3_miss_local_dram.snoop_missoffcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000010offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000080offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000122umask=0x2,period=2000003,cmask=4,event=0xb1L3 Lookup any request that access cache and found line in MESI-stateunc_clock.socket( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) )This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dramCounts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dramoffcore_response.all_reads.llc_miss.any_responseumask=0x4,event=0umask=0x40,period=200000,event=0x23umask=0x70,period=200000,event=0x27umask=0x42,period=200000,event=0x2dl2_rqsts.self.any.e_statel2_reject_busq.self.prefetch.mesiSIMD saturated arithmetic micro-ops executedumask=0x80,period=2000000,event=0xb1SIMD saturated arithmetic micro-ops retiredsimd_uop_type_exec.shift.arsimd_uop_type_exec.arithmetic.sumask=0x8,period=2000000,event=0xc7misalign_mem_ref.st_split.arumask=0xe0,period=200000,event=0x69Burst (full cache-line) bus transactionsumask=0x2b,period=200000,event=0x77reissue.anybr_inst_type_retired.indOnly taken macro conditional branch instructionsDTLB misses due to store operationsNumber of D-side only page walksLocked load uops retired (Precise event capable)  Supports address when precise (Must be precise)offcore_response.partial_streaming_stores.l2_miss.anyCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200001000Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000004Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines that miss the L2 cacheoffcore_response.demand_data_rd.l2_miss.hitm_other_coreCounts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitectureumask=0x2,period=200003,event=0xcaCounts the number of floating point divide uops retired (Must be precise)umask=0x4,period=200003,event=0xc3umask=0xf9,period=200003,event=0xc4Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise)BACLEARs asserted for conditional branchumask=0x13,period=200003,event=0xd0Counts data reads generated by L1 or L2 prefetchers hit the L2 cacheCounts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystemPage walk completed due to an instruction fetch in a 1GB pageThis event counts requests originating from the core that reference a cache line in the last level cacheDemand data read requests that access L2 cacheNumber of times HLE lock could not be elided due to ElisionBufferAvailable being zeroumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00122offcore_response.demand_rfo.l3_miss.any_responseExecution stalls due to memory subsystemCounts number of cycles no uops were dispatched to be executed on this thread  Spec update: HSD144, HSD30, HSM31umask=0x21,event=0x22Unit: uncore_cbox An external snoop hits a modified line in some processor coreThis event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walksCompleted page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G)Counts the number of Extended Page Table walks from the DTLB that hit in the L3page_walker_loads.ept_itlb_l1page_walker_loads.ept_itlb_l3Retired load uops missed L3. Excludes unknown data source   Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F800091Number of near taken branches retired (Precise event)l2_l1d_wb_rqsts.hit_eMiss in last-level (L3) cache. Excludes Unknown data-source (Precise event)mem_load_uops_llc_hit_retired.xsnp_hitumask=0x2,period=100003,event=0xf2umask=0x20,period=100003,event=0xc1offcore_response.data_in_socket.llc_miss.local_dramCycles with pending L2 miss loads. Set AnyThread to count per coreunc_cbo_xsnp_response.invalunc_cbo_cache_lookup.iUnit: uncore_cbox LLC lookup request that access cache and found line in I-stateFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsDemand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page sizeumask=0x82,period=100003,event=0x8mem_load_uops_llc_miss_retired.remote_fwdCounts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00010LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable. Unit: uncore_cbox LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode.code. Unit: uncore_cbox Occupancy for all LLC misses that are addressed to local memory. Unit: uncore_cbox l2_l1d_wb_rqsts.hit_sThis event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accessesCases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limitumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400077umask=0x2,period=2000003,event=0xa2This event counts the number of Uops issued by the front-end of the pipeilne to the back-endNumber of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)ld_blocks_partial.all_sta_blockmem_uops_retired.l1_miss_loadsumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080044Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l1_data_rd.l2_hit_far_tile_mCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x00020032f7umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000004Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000044Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_software.l2_hit_this_tile_sumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008008000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000044offcore_response.pf_software.l2_hit_this_tile_foffcore_response.demand_code_rd.l2_hit_far_tileCounts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstandingCounts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080201000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200020offcore_response.demand_data_rd.mcdram_nearCounts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Faroffcore_response.partial_writes.mcdramCounts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP (Precise event)Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multipliesbr_misp_retired.rel_callumask=0x1,period=100003,edge=1,event=0x5L1 data cache readsl1d_prefetch.missl2_data_rqsts.prefetch.s_stateumask=0x2,period=100000,event=0xf1L2 lines evictedL2 demand store RFOs in I state (misses)umask=0x1,period=2000000,event=0xbMemory instructions retired above 4096 clocks (Precise Event)Offcore data reads satisfied by any cache or DRAMoffcore_response.any_data.any_locationOffcore code reads satisfied by the IO, CSR, MMIO unitoffcore_response.any_ifetch.remote_cacheOffcore requests satisfied by the LLC and not found in a sibling coreoffcore_response.any_rfo.any_locationOffcore RFO requests satisfied by the LLC and HIT in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4722Offcore writebacks to the LLC  and HITM in a sibling coreAll offcore code or data read requestsOffcore code or data read requests satisfied by the LLC or local DRAMOffcore code or data read requests that HIT in a remote cacheoffcore_response.demand_data.any_locationoffcore_response.demand_data_rd.llc_hit_other_core_hitmOffcore demand code reads satisfied by the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x804Offcore demand RFO requests satisfied by a remote cacheoffcore_response.pf_data.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8010offcore_response.pf_data_rd.local_cacheOffcore prefetch data reads satisfied by a remote cacheoffcore_response.pf_rfo.local_cacheOffcore prefetch requests satisfied by any cache or DRAMOffcore prefetch requests satisfied by the LLCumask=0x40,period=2000000,event=0x10umask=0x2,period=200000,event=0x12128 bit SIMD integer unpack operationsSIMD integer 64 bit pack operationsOffcore writebacks to any DRAMOffcore prefetch data requests satisfied by any DRAMOffcore prefetch data reads satisfied by the local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6070L1I instruction fetch hitsumask=0x7,period=2000000,event=0x13br_misp_exec.near_callsbr_misp_exec.takenRegen stall cyclesumask=0x1,period=2000000,event=0x18umask=0x80,period=2000000,event=0xa2Uops executed on ports 0-4 (core count)inv=1,umask=0x3f,any=1,period=2000000,cmask=1,event=0xb1Uops executed on port 2 (core count)umask=0x8,any=1,period=2000000,event=0xb1umask=0x1,any=1,period=2000000,cmask=1,event=0xeuops_retired.active_cyclesumask=0x2,period=2000000,event=0xc2ITLB missCounts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoMoffcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwdoffcore_response.other.l4_hit_local_l4.snoop_hit_no_fwdoffcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040002Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)offcore_response.demand_code_rd.l3_hit_e.snoop_hitmperiod=200003,umask=0x24,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080002offcore_response.other.l3_hit_s.snoop_not_neededoffcore_response.demand_data_rd.l4_hit_local_l4.snoop_missmem_load_misc_retired.ucoffcore_response.demand_code_rd.l4_hit_local_l4.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080002Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.offcore_response.other.l3_hit_s.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001C0004Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event)cmask=2,period=2000003,umask=0x1,event=0x9ccmask=4,period=2000003,umask=0x18,event=0x79cmask=1,period=2000003,umask=0x1,event=0x9cperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C408000Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x20001C0004offcore_response.demand_rfo.l3_miss.snoop_hitmoffcore_response.demand_code_rd.l3_miss.any_snoopCounts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)period=2000003,umask=0x1,event=0xb1Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6exe_activity.3_ports_utilThis event counts taken branch instructions retired  Spec update: SKL091 (Precise event)period=2000003,umask=0x40,event=0xccCounts cycles during which no uops were executed on all ports and Reservation Station (RS) was not emptyRetirement slots usedNumber of macro-fused uops retired. (non precise)period=2000003,umask=0x2,event=0xa6Cycles total of 1 uop is executed on all ports and Reservation Station was not emptyperiod=400009,umask=0x1,event=0xc5Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear eventsThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoidedBranch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)period=100003,umask=0x2,event=0x85Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultCounts the number of DTLB flush attempts of the thread-specific entriesperiod=100003,umask=0x1,event=0x85This event counts the number of load ops retired that got data from the other core or from the other module (Precise event)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000044Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedREL_CALL counts the number of near relative CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of RETURN baclearsRetired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event)offcore_response.all_code_rd.llc_hit.hitm_other_coreCounts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean responseREQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8ffumask=0x1,period=100000,event=0xb7,offcore_rsp=0x208REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIOoffcore_response.demand_rfo.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x450offcore_response.pf_data.local_dram_and_remote_cache_hitoffcore_response.data_ifetch.other_local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf880umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3050REQUEST = PREFETCH and RESPONSE = REMOTE_DRAMsnoopq_requests.codeumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2701Retired loads that hit remote socket in modified state (Precise Event)Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts prefetch (that bring data to L2) data reads that hit in the L3Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000002offcore_response.pf_l2_rfo.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00020Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cacheCounts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dramBranches;InsTypeAverage IO (network or disk) Bandwidth Use for Reads [GB / sec]SoCumask=0x1,event=0x4Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read.  This event only counts regular reads and does not includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or notuncore otherunc_cha_hitme_hit.ex_rdsumask=0x04,event=0x37Snoop filter capacity evictions for E-state entries. Unit: uncore_cha PCIe Completion Buffer occupancy of completions with data: Part 0. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 0Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc0Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_write.part0unc_iio_txn_req_by_cpu.peer_write.part2Read request for up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Write request of up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busCounts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x84Total IRP occupancy of inbound read and write requests.  This is effectively the sum of read occupancy and write occupancyunc_m2m_directory_update.i2aunc_m2m_imc_writes.allBL Ingress (from CMS) Occupancyunc_m2m_txc_bl_occupancy.allCount cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0491offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_e.no_snoop_neededoffcore_response.all_pf_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C07F7offcore_response.all_reads.l3_hit_f.hitm_other_coreoffcore_response.all_reads.l3_hit_s.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01004007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000207F7This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONEoffcore_response.all_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_neededoffcore_response.demand_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.other.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080208000offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_f.no_snoop_neededoffcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200100offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_noneocr.all_data_rd.l3_miss_local_dram.any_snoopOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000120ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_coreOCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000122ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000004ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwdocr.demand_data_rd.l3_miss_local_dram.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000002ocr.demand_rfo.l3_miss.no_snoop_neededCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITMocr.demand_rfo.l3_miss_local_dram.snoop_noneocr.other.l3_miss.hit_other_core_fwdocr.other.l3_miss.snoop_missocr.other.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORECounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000080ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_noneocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000080Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss.no_snoop_neededoffcore_response.demand_code_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_rfo.l3_miss.hitm_other_coreoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_neededocr.all_data_rd.l3_hit.snoop_hit_with_fwdOCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_pf_data_rd.l3_hit.snoop_noneOCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_f.any_snoopOCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONEOCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDOCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_s.snoop_missOCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOPocr.all_pf_rfo.l3_hit_f.no_snoop_neededOCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_pf_rfo.supplier_none.hitm_other_coreOCR.ALL_READS.L3_HIT_F.SNOOP_NONEOCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_S.HITM_OTHER_COREOCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONEOCR.ALL_RFO.L3_HIT_S.SNOOP_NONEocr.demand_code_rd.l3_hit_m.hit_other_core_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOPocr.demand_data_rd.l3_hit.hit_other_core_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOPCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.demand_rfo.l3_hit.snoop_missCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOPCounts any other requests OCR.OTHER.L3_HIT.SNOOP_NONEocr.other.l3_hit_s.any_snoopocr.other.pmm_hit_local_pmm.snoop_not_neededocr.pf_l1d_and_sw.supplier_none.no_snoop_neededCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOPCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONECounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l2_rfo.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISSocr.pf_l3_data_rd.l3_hit_e.snoop_noneocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOPocr.pf_l3_rfo.l3_hit_s.hitm_other_coreCycles where DRAM ranks are in power down (CKE) mode+C37. Unit: uncore_imc Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_tagchk.miss_cleanunc_m_tagchk.miss_dirtyTOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsCounts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completionperiod=100003,umask=0x4,event=0xc7Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)icl metricsuops_retired.slots / inst_retired.anySpeculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional readsCounts demand data reads that DRAM supplied the requestocr.hwpf_l2_rfo.l3_hit.anyCounts the number of PREFETCHT0 instructions executedCounts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of responsecmask=1,inv=1,period=1000003,umask=0x1,event=0xc0period=2000003,umask=0x2,event=0x63Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responsesThis event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD  Supports address when precise (Precise event)False dependencies due to partial compare on addressunc_cha_tor_inserts.ioumask=0xC001FF04,event=0x35unc_cha_tor_occupancy.ia_missTOR Occupancy : All requests from iA Cores that Missed the LLC. Unit: uncore_cha TOR Occupancy : RFOs issued by iA Cores. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha fc_mask=0x07,ch_mask=0x10,umask=0x80,event=0x84fc_mask=0x04,umask=0x10,event=0xd5Misc Events - Set 1 : Lost Forward. Unit: uncore_irp uncore_m2pcieClockticks in the UBOX using a dedicated 48-bit Fixed Counter. Unit: uncore_ubox umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000001period=200003,event=0xc4umask=0xC8A7FE01,event=0x35period=200003,umask=0x4,event=0x34topdown_fe_bound.icacheCounts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same lineCounts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clearsperiod=1000003,event=0x74topdown_be_bound.reorder_buffertopdown_fe_bound.allperiod=1000003,event=0x71Counts the total number of instructions retired. (Fixed event) (Precise event)Counts the number of first level TLB misses but second level hits due to loads that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLBCounts the number of page walks due to storse that miss the PDE (Page Directory Entry) cacheperiod=2000003,umask=0x4,event=0x4fCounts the number Extended Page Directory Pointer Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesCounts the number of memory retired ops that missed in the second level TLB  Supports address when precise (Precise event)IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another corel2_request_g1.l2_hw_pfumask=0x40,event=0x63Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2l2_pf_miss_l2_hit_l3umask=0xff,event=0x71l3_comb_clstr_state.other_l3_miss_typsevent=0xc5ex_tagged_ibs_ops.ibs_count_rolloverumask=0x38,event=0x147Total number of fp uOps on pipe 2Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass)SSE bottom-executing uOps retiredumask=0x01,event=0x4bCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailableall_dc_accessesL2 Cache Hits from L1 Data Cache Missesl2_cache_hits_from_l2_hwpf(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typsThe number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB pageMultiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15umask=0x08,event=0xeumask=0x02,event=0x25LS MAB Allocates by Type. LoadsL1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLBCount of dispatched Ops from DecoderRetired lock instructions. Comparable to legacy bus lockCounts the number of SMIs receivedDemand Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_hw_pf_dc_fills.mem_io_remotede_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stallumask=0x14,event=0x44FR_DISPATCH_STALL_FOR_SERIALIZATIONMEM_ERRORTTBR_WRITEL1_DCACHE_HASH_MISSL1_DCACHE_NEON_CACHEABLEEVENT_79HEVENT_89HEVENT_9BHEVENT_9FHEVENT_A8HEVENT_EAHEVENT_ECHMAIN_EXECUTION_UNIT_PIPEL2D_CACHE_LDL1I_TLBMEM_CAP_WRITEL2CACHEMASTER_WRITE_REQINTEGER_MULDIV_COMPLETEDL2_IMISS_STALL_CYCLESCPO_READ_STALLSREQUEST_COUNTKILLED_FETCH_SLOTSMDU_DSP_SATURATION_INSNSGRADUATION_REPLAYSREFRESHED_DSTSFP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSULOAD_INSTR_COMPLETEDFIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLYFPR_ISSUE_QUEUE_ENTRIESMARKED_GROUP_COMPLETEDCR_MARKED_INSTR_FINISHFXU_MARKED_INSTR_FINISHEDLOAD_UOPS_COMPLETEDCYCLES_SU2_SCHED_STALLEDMISALIGNED_LOAD_STORE_ACCESS_TRANSLATEDBIU_MASTER_DATA_SIDE_REQUESTSDLFB_LOAD_MISS_CYCLESSTORE_RETRIESDVT1_DETECTEDunhalted-cyclesedgelow-op-pos-2SOFT-CLOCK.HARDINTERRUPTTAGGINGINTEL_XSCALEex_ret_brn"0x%016jx", v10GenuineIntel-6-55-[01234]1 / inst_retired.any / cycles(cstate_pkg@c6\-residency@ / msr@tsc@) * 100umask=0x44,period=200003,event=0x24This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetchesRequests from L2 hardware prefetchersThis event counts the number of WB requests that hit L2 cacheumask=0x1,any=1,cmask=1,period=2000003,event=0x48This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_responsemem_load_uops_retired.l1_hitumask=0x2,period=100003,event=0xd1umask=0x2,period=20011,event=0xd2This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Supports address when precise.  Spec update: BDE70, BDM100mem_load_uops_l3_miss_retired.remote_draml2_trans.all_requestsL2 cache lines in S state filling L2Split locks in SQNumber of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?fp_arith_inst_retired.packedThis event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist interventionThis event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_mite_uopsumask=0x40,period=2000003,event=0x54Loads with latency value being above 4  Spec update: BDM100, BDM35 (Must be precise)This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS)umask=0x1,period=1000003,event=0x58This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunkbr_inst_exec.all_direct_jmpumask=0x10,any=1,period=2000003,event=0xa1Cycles per core when uops are exectuted in port 4uops_executed.cycles_ge_4_uops_execumask=0x2,cmask=3,period=2000003,event=0xb1This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: BDM61umask=0x20,period=400009,event=0xc51llc_references.pcie_readumask=0xC,event=0x1llc_misses.mem_readfreq_max_power_cycles %Code miss in all TLB levels causes a page walk that completes. (2M/4M)  Spec update: BDM69umask=0x8,period=100003,event=0x85This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles)Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)IpLFloating Point Operations Per CycleMemory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Spec update: BDM100, BDE70.  Supports address when precise (Precise event)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Spec update: BDE70, BDM100.  Supports address when preciseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0001Counts all demand code readsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010020offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwdoffcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwdoffcore_response.pf_l3_rfo.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020100Counts any other requests have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080028000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100028000offcore_response.all_pf_rfo.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020091offcore_response.all_data_rd.l3_hit.snoop_noneumask=0x1,period=2000003,cmask=3,event=0x9cCounts randomly selected loads with latency value being above four  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000008offcore_response.pf_l2_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104008000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84008000offcore_response.all_pf_data_rd.l3_hit.snoop_non_dramoffcore_response.all_pf_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000120offcore_response.all_data_rd.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000122Unit: uncore_cbox L3 Lookup read request that access cache and found line in I-stateumask=0x02,event=0x81Unit: uncore_arb Number of Writes allocated - any write transactions: full/partials writes and evictionsThis event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement  Supports address when precise (Precise event)offcore_response.demand_rfo.llc_hit.hitm_other_coreCounts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_data_rd.llc_miss.remote_hit_forwardumask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC00091offcore_response.pf_llc_rfo.llc_miss.any_responseActually retired uops  Supports address when precise (Precise event)Retirement slots used (Precise event)Direct and indirect near call instructions retired (Precise event)L2 cache missesl2_lines_in.self.demandL2 cache readsumask=0x78,period=200000,event=0x29l2_ld.self.demand.e_stateumask=0x41,period=200000,event=0x29umask=0x41,period=200000,event=0x2cumask=0x41,period=200000,event=0x30l1d_cache.all_refumask=0x48,period=200000,event=0x40fp_assist.arSIMD micro-ops executed (excluding stores)umask=0x4,period=2000000,event=0xb3Memory references that cross an 8-byte boundary (At Retirement)Nonzero segbase 1 bubbleumask=0x81,period=200000,event=0x7segment_reg_loads.anyNumber of thermal tripsumask=0x21,period=200000,event=0x77Bus queue is emptyIO requests waiting in the bus queuebr_inst_type_retired.dir_callbr_inst_retired.mispreddata_tlb_misses.dtlb_miss_stumask=0x42,period=200003,event=0xd0Memory uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Memory uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that hit in the L2 cache  Supports address when precise (Must be precise)Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredoffcore_response.streaming_stores.l2_miss.anyumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004800umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004000offcore_response.full_streaming_stores.l2_miss.hitm_other_coreCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredoffcore_response.demand_data_rd.l2_hitMS decode startsCycles code-fetch stalled due to any reasonCycles pending interrupts are maskedumask=0x8,period=2000003,event=0xc2Machine clears due to memory disambiguationCounts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise)umask=0x1,period=200003,event=0xcdCounts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progressCounts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013091Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultumask=0x10,period=200003,event=0x49Dirty L2 cache lines evicted by demandCycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135Cycles with less than 3 uops delivered by the front end  Spec update: HSD135Number of times an HLE execution aborted due to incompatible memory type  Spec update: HSD65Number of times an RTM execution aborted due to incompatible memory type  Spec update: HSD65offcore_response.all_rfo.l3_miss.local_dramCounts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttlingNumber of integer move elimination candidate uops that were not eliminatedunc_cbo_xsnp_response.hitm_externalumask=0x4f,event=0x34unc_arb_coh_trk_occupancy.allCode miss in all TLB levels causes a page walk that completes. (2M/4M)Number of DTLB page walker loads that hit in the L3  Spec update: HSD25umask=0x28,period=2000003,event=0xbcNumber of ITLB page walker loads from memory  Spec update: HSD25umask=0x10,period=100003,event=0xd3umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00010RFOs that miss cache linesCounts all demand & prefetch code reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10800Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a sarith.fpu_divCounts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cyclesNumber of self-modifying-code machine clears detectedUnit: uncore_cbox A snoop hits a modified line in some processor coreFilter on cross-core snoops initiated by this Cbox due to LLC evictionData forwarded from remote cacheCounts prefetch data reads that hit in the LLC and sibling core snoop returned a clean responseCounts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20010Counts prefetch (that bring data to L2) data reads that miss in the LLCCounts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dramItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read. Unit: uncore_cbox Number of non data (control) flits transmitted . Unit: uncore_qpi unc_p_freq_band3_transitionsCounts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu freq_max_current_cycles %unc_p_freq_ge_4000mhz_cyclesRetired load uops that miss the STLB (Precise event)umask=0x2,period=2000003,event=0xacoffcore_response.all_demand_mlc_pref_reads.llc_miss.local_draminsts_written_to_iq.instsCounts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cyclesumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400044offcore_response.any_code_rd.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010044offcore_response.any_request.l2_hit_near_tile_mCounts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts Full streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.bus_locks.l2_hit_far_tile_mCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000001umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002008000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000044offcore_response.bus_locks.l2_hit_this_tile_eCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S stateCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010003091offcore_response.any_code_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400040umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00802032f7offcore_response.any_data_rd.mcdram_nearoffcore_response.pf_software.ddr_nearCounts Bus locks and split lock requests that accounts for data responses from DRAM LocalCounts L2 code HW prefetches that accounts for data responses from DRAM Localoffcore_response.pf_l2_rfo.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400004Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000002Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)offcore_response.any_rfo.mcdramCounts the number of branch instructions retired that were conditional jumps and predicted taken (Precise event)Counts the number of near CALL branch instructions retired (Precise event)Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code pageumask=0x1,period=200000,event=0x4el1d_wb_l2.e_stateumask=0xff,period=200000,event=0x26l2_data_rqsts.prefetch.e_stateumask=0x1,period=100000,event=0xf2L2 prefetch hitsL1D writeback to L2 transactionsumask=0x2,period=200000,event=0xf0l2_write.lock.e_statel2_write.rfo.s_stateumask=0x10,period=10000,event=0xfMemory instructions retired above 256 clocks (Precise Event)umask=0x10,period=3,event=0xb,ldlat=0x8000Offcore data reads satisfied by the LLC and HIT in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x811offcore_response.any_request.any_cache_dramoffcore_response.any_request.llc_hit_other_core_hitOffcore RFO requests satisfied by a remote cache or remote DRAMOffcore demand data requests satisfied by the IO, CSR, MMIO unitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1803Offcore demand RFO requests satisfied by the LLC or local DRAMOffcore other requests satisfied by the LLC or local DRAMOffcore other requests that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x130Offcore prefetch data requests satisfied by a remote cacheOffcore prefetch data reads that HIT in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4740offcore_response.pf_rfo.remote_cache_hitoffcore_response.prefetch.io_csr_mmiofp_comp_ops_exe.sse_fp_scalarSSE FP scalar UopsSSE* FP single precision Uops128 bit SIMD integer pack operationsumask=0x40,period=200000,event=0x12macro_insts.decodedOffcore RFO requests satisfied by any DRAMOffcore demand code reads that missed the LLCoffcore_response.demand_ifetch.local_dramOffcore demand code reads satisfied by a remote DRAMOffcore prefetch data reads that missed the LLCOffcore prefetch code reads satisfied by a remote DRAMLoads dispatched from stage 305Partial register stall cyclesSuper Queue full stall cyclesMispredicted conditional branches executedild_stall.mruresource_stalls.rob_fullinv=1,umask=0x1,period=2000000,cmask=1,event=0xc2dtlb_load_misses.pde_missDTLB load miss caused by low part of addressoffcore_response.other.l3_hit_s.snoop_hit_no_fwdoffcore_response.demand_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040048000mem_load_retired.l1_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100108000offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100088000offcore_response.other.l3_hit.spl_hitoffcore_response.demand_rfo.l4_hit_local_l4.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020002period=100003,umask=0x41,event=0xd0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0080002period=2000003,umask=0x4,event=0xc7period=2000003,umask=0x20,event=0xc7Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x300206Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event)icache_64b.iftag_missCycles with at least 6 Demand Data Read requests that miss L3 cache in the superQNumber of times an HLE execution aborted due to hardware timer expirationperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000004Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycleperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000020001Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise (Must be precise)period=1009,umask=0x1,event=0xcd,ldlat=0x80period=2000003,umask=0x40,event=0x54cycle_activity.stalls_l3_missCore cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear eventCycles total of 3 uops are executed on all ports and Reservation Station was not emptyThis event counts cycles during which the microcode scoreboard stalls happenCounts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct pathNumber of uops delivered to the back-end by the LSD(Loop Stream Detector)This event counts conditional branch instructions retired  Spec update: SKL091 (Precise event)Cycles total of 2 uops are executed on all ports and Reservation Station was not emptyThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPUarb@event\=0x80\,umask\=0x2@ / arb@event\=0x80\,umask\=0x2\,cmask\=1@MEM_Parallel_ReadsCode miss in all TLB levels causes a page walk that completes. (1G)Store misses in all TLB levels causes a page walk that completes. (All page sizes)rehabq.st_splitsCounts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cacheThis event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processorsThis event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event)offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dramREQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_l_ifetch.llc_miss_local.dramMispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event)REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATIONREQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATIONREQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITMREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PREFETCH and RESPONSE = IO_CSR_MMIOREQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAMREQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDoffcore_response.prefetch.other_local_dramsnoopq_requests_outstanding.code_not_emptyumask=0x4,period=20000,event=0xc5umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5833umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5850umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5870umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF850mem_uncore_retired.local_dram_and_remote_cache_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0491Counts all prefetch data reads that hit in the L3offcore_response.pf_l1d_and_sw.l3_hit.any_snoopCounts all prefetch (that bring data to L2) RFOs that hit in the L3offcore_response.pf_l3_data_rd.l3_hit.no_snoop_neededNumber of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts all demand & prefetch data reads that miss in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00491offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00004Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwdoffcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dramCounts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cacheCounts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dramCounts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or notCounts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller).  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???umask=0x21,event=0x35,config1=0x40040e33umask=0x21,event=0x35,config1=0x41833UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data. Unit: uncore_upi ll fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83umask=0x82,event=0x33unc_cha_snoop_resp.rspifwdCounts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busPeer to peer read request for 4 bytes made by a different IIO unit to IIO Part1. Unit: uncore_iio unc_iio_data_req_by_cpu.peer_write.part0Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part0fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc1Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc1Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busCounts cycles when direct to core mode (which bypasses the CHA) was disabledWrites to iMC issued. Unit: uncore_m2m Inserts into the Memory Controller Prefetch Queue. Unit: uncore_m2m umask=0x4,event=0x31Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unitThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080122This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_s.hit_other_core_fwdoffcore_response.all_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020122This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.demand_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOPoffcore_response.other.l3_hit_e.hit_other_core_no_fwdoffcore_response.other.pmm_hit_local_pmm.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040400offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwdoffcore_response.pf_l2_rfo.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400100offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020100MemoryBW;SoC;Serverperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000491OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITMOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEOCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08100007F7ocr.all_rfo.l3_miss.snoop_noneCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss_local_dram.any_snoopocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_missCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss.remote_hitmCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C008000Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDEDocr.other.l3_miss.remote_hit_forwardperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B808000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210008000Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOPCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000020ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000020ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONEocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_missoffcore_response.demand_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwdOCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_f.hit_other_core_fwdOCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONEocr.all_data_rd.l3_hit_m.any_snoopocr.all_data_rd.l3_hit_s.snoop_missOCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_data_rd.supplier_none.no_snoop_neededOCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONEOCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDOCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISSocr.all_reads.any_responseocr.all_reads.l3_hit.no_snoop_neededocr.all_reads.l3_hit_s.hitm_other_coreOCR.ALL_RFO.ANY_RESPONSE have any response typeocr.all_rfo.l3_hit_s.hit_other_core_fwdOCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwdocr.demand_rfo.l3_hit.snoop_noneocr.demand_rfo.l3_hit_e.any_snoopocr.demand_rfo.l3_hit_e.no_snoop_neededocr.other.l3_hit.hit_other_core_fwdocr.other.l3_hit_f.any_snoopocr.other.l3_hit_s.hit_other_core_fwdocr.other.supplier_none.any_snoopocr.pf_l2_data_rd.supplier_none.no_snoop_neededocr.pf_l2_rfo.any_responseocr.pf_l2_rfo.l3_hit_m.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONECounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOPCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.supplier_none.no_snoop_neededumask=0x21,event=0x36,config1=0x40433Counts the number of cache lines replaced in L1 data cacheCounts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeRetired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)l2_rqsts.swpf_hitperiod=100003,umask=0x1,event=0xc7assists.fpRetired instructions after front-end starvation of at least 2 cycles (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x520006period=100003,umask=0x1,event=0x54Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)period=100003,umask=0x10,event=0x54period=100003,umask=0x4,event=0xc9Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the requestCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.hwpf_l3.l3_hit.anyNumber of uops executed on port 2 and 3Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event)Number of instructions retired. General Counter - architectural event (Precise event)period=100003,umask=0x8,event=0xa2period=50021,umask=0x20,event=0xc5cmask=1,edge=1,inv=1,period=100003,umask=0x1,event=0x5eperiod=2000003,umask=0x2,event=0xecThis event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthreadperiod=50021,umask=0x11,event=0xc5Counts conditional branch instructions retired (Precise event)Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycleumask=0x01,event=0x20TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts; DRd Pref misses from local IA. Unit: uncore_cha TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_remote_pmmfc_mask=0x07,ch_mask=0x08,umask=0x80,event=0x84unc_iio_data_req_of_cpu.mem_write.part7fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0xc1unc_iio_txn_req_of_cpu.mem_read.part5fc_mask=0x04,umask=0xff,event=0xd5unc_m3upi_clockticksValid Flits Received : All Data. Unit: uncore_upi ll Counts the number of store uops retired  Supports address when precise (Precise event)Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0period=200003,umask=0x2,event=0xe6topdown_bad_speculation.monuketopdown_be_bound.mem_schedulerCounts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branchesCounts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS)period=1000003,umask=0x80,event=0x71Counts the total number of mispredicted branch instructions retired for all branch types (Precise event)Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page faultperiod=200003,umask=0x10,event=0x49branchL2 BTB CorrectionLS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requestsCycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2xi_sys_fill_latencyex_ret_brn_tkndram_channel_data_controller_2The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2umask=0x07,event=0x2fp_ret_sse_avx_ops.dp_mult_add_flopsfp_ret_sse_avx_ops.dp_mult_flopsls_dc_accessesumask=0x01,event=0x52de_dis_dispatch_token_stalls0.alsq3_0_token_stallAll L1 Data Cache AccessesL2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)1core clocks3e-5MiBnps1_die_to_dramfp_disp_faults.ymm_fill_faultNumber of interrupts takenevent=0x2dumask=0x02,event=0x43Demand Data Cache Fills by Data Source. Local L2 hitde_dis_uops_from_decoder.decoder_dispatchedde_dis_dispatch_token_stalls1.fp_misc_rsrc_stallThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M pageex_ret_ind_brch_instrls_any_fills_from_sys.ext_cache_remoteumask=0x01,event=0x47This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 availableNB_SIZED_COMMANDSL2_CACHE_ACCESSEVENT_0CHEVENT_1EHEVENT_20HEVENT_40HEVENT_56HEVENT_C9HEVENT_CAHEVENT_D0HEVENT_F7HDMB_SPECEXC_DABORTSTREX_SPECDCACHE_WRITE_HITL2CACHEMASTER_WRITE_REQ_FLITTAGCACHEMASTER_WRITE_RSPITLB_MISSESMISPREDICTED_BRANCH_INSNS_CYCLESDISSUEIUNAPMON_SIGVPU_INSTR_WAIT_CYCLESL1_DATA_PUSHESL2_TOUCH_HITSMARKED_GROUP_DISPATCHGCT_EMPTY_BY_BRANCH_MISS_PREDICTSTORE_NO_REAL_ADDRSTORES_TRANSLATEDDATA_L1_CACHE_LOCKSDATA_MMU_BUSY_CYCLESINSTR_L1_CACHE_RELOADSBIU_MASTER_REQUESTSILFB_FETCH_MISS_CYCLESCRIT_INPUT_INTR_PENDING_LATENCY_CYCLESINTV_ALLOCATIONSSTASH_HIT_DLFBL2_CLEAN_LINE_INVALIDATIONSIAC2S_DETECTEDDVT4_DETECTEDFPU_FPSCR_FULL_STALLdsdc-filldataCASCADEINTEL_BROADWELL_XEONMIPS_OCTEONFREEDELETEDps->ps_len == 0/usr/src/lib/libpmc/libpmc_pmu_util.cLLC-MISSESany{"type": "pmcattach"%s, "pid": "%d", "flags": "0x%08x", "pcomm": "%s"}
GenuineIntel-6-1AInstructions Per Cycle (per logical thread)DSB_Coveragel1d_pend_miss.pending / ( cpu@l1d_pend_miss.pending_cycles\,any\=1@ / 2) if #smt_on else l1d_pend_miss.pending_cyclesSMT_2T_Utilizationumask=0x24,period=200003,event=0x24umask=0x3f,period=200003,event=0x24Demand requests to L2 cacheThis event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replaceoffcore_requests_outstanding.demand_data_rd_ge_6umask=0x2,period=2000003,event=0x60umask=0x8,period=2000003,event=0x60offcore_requests_outstanding.cycles_with_data_rdumask=0x1,period=2000003,event=0xb2Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transactionmem_uops_retired.all_loadsL2 or L3 HW prefetches that access L2 cacheL1D writebacks that access L2 cachel2_lines_in.eL2 cache lines in E state filling L2fp_arith_inst_retired.256b_packed_doubleedge=1,umask=0x10,cmask=1,period=2000003,event=0x79idq.all_mite_cycles_any_uopsicache.hiticache.missesNumber of times a TSX Abort was triggered due to an evicted line caused by a transaction overflowNumber of times HLE aborted and was not due to the abort conditions in subevents 3-6mem_trans_retired.load_latency_gt_16uops_issued.anyReference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)cpu_clk_unhalted.ref_xclk_anyuop_dispatches_cancelled.simd_prfCounts the number of uops to be executed per-thread each cycleumask=0x1,cmask=4,period=2000003,event=0xb1Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event)Not taken branch instructions retiredumask=0x1,event=0x35,filter_opc=0x18dread requests to remote home agent. Unit: uncore_ha (unc_p_freq_trans_cycles / unc_p_clockticks) * 100.dtlb_load_misses.walk_durationumask=0x10,period=100003,event=0x85umask=0x20,period=100003,event=0x85umask=0x60,period=100003,event=0x85page_walker_loads.dtlb_memoryThis event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on)inst_retired.any / mem_uops_retired.all_loadsBranches;Instruction_Type( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))L1 cache true misses per kilo instruction for retired demand loadsThis is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path  Spec update: BDM35.  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0001offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwdCounts writebacks (modified to exclusive) have any response typeoffcore_response.pf_l2_rfo.supplier_none.snoop_hitmoffcore_response.pf_l2_rfo.l3_hit.any_snoopoffcore_response.pf_l2_code_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0100Counts prefetch (that bring data to LLC only) code reads have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020200offcore_response.pf_l3_code_rd.l3_hit.snoop_not_neededoffcore_response.other.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0090output - Numeric Overflow, Numeric Underflow, Inexact Result  (Precise Event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0002offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000100offcore_response.pf_l3_rfo.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000122offcore_response.all_rfo.l3_miss.snoop_hit_no_fwdUnit: uncore_cbox A cross-core snoop resulted from L3 Eviction which misses in some processor coreUnit: uncore_cbox L3 Lookup write request that access cache and found line in MESI-stateUnit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-stateumask=0x01,event=0x80Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_rfo.llc_hit.hitm_other_coreCounts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_rfo.llc_miss.any_responseoffcore_response.pf_llc_code_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00100unc_q_clockticksumask=0x40,period=200000,event=0x27umask=0x41,period=200000,event=0x28l2_ifetch.self.mesiumask=0x4f,period=200000,event=0x28umask=0x48,period=200000,event=0x2aumask=0x44,period=200000,event=0x2bL2 locked accessesumask=0x42,period=200000,event=0x30Cycles no L2 cache requests are pendingmem_load_retired.l2_hitx87_comp_ops_exe.any.sSIMD micro-ops retired (excluding stores) (Must be precise)umask=0x10,period=2000000,event=0xb3umask=0xa0,period=2000000,event=0xb3Retired Streaming SIMD Extensions (SSE) scalar-single instructionsprefetch.software_prefetchumask=0x20,period=200000,event=0x61bus_trans_rfo.selfext_snoop.all_agents.hitmumask=0x1,period=2000000,event=0xc6umask=0x81,period=200000,event=0x2data_tlb_misses.l0_dtlb_miss_stpage_walks.d_side_walksCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_hitumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003010Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cacheoffcore_response.corewb.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000008umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000001Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor moduleCounts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or notumask=0x0,period=2000003,event=0xc2Uops retired (Precise event capable) (Must be precise)umask=0x1,period=200003,event=0xc3umask=0x0,period=200003,event=0xc4br_misp_retired.returnRetired mispredicted near indirect call instructions (Precise event capable) (Must be precise)Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branchesumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cacheoffcore_response.demand_code_rd.l2_miss.hitm_other_coreCounts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000012000Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000022ept.walk_pendingDemand data read requests sent to uncore  Spec update: HSD78Retired load uops with locked access. (precise Event)  Spec update: HSD76, HSD29, HSM30.  Supports address when precise (Precise event)Retired store uops that split across a cacheline boundary. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)umask=0x20,period=100003,event=0xd1Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Spec update: HSM30.  Supports address when precise (Precise event)Counts all prefetch (that bring data to LLC only) code reads hit in the L3Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedIncrement each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cyclesicache.ifetch_stallSpeculative cache-line split store-address uops dispatched to L1Doffcore_response.all_code_rd.l3_miss.any_responseThis event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etcarith.divider_uopsumask=0x2,period=2000003,event=0x14Number of SIMD move elimination candidate uops that were not eliminatedThis event counts cycles during which no instructions were allocated because no Store Buffers (SB) were availableCode miss in all TLB levels causes a page walk that completes. (4K)page_walker_loads.ept_dtlb_l3umask=0x44,period=2000003,event=0xbcRetired load uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00091Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cyclesDirty L2 cache lines evicted by the MLC prefetcheroffcore_response.demand_code_rd.llc_hit.no_snoop_neededCounts all demand data reads that hit in the LLCNumber of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycleNumber of transitions from AVX-256 to legacy SSE when penalty applicablepage_walks.llc_missLoads with latency value being above 512 (Must be precise)Cycles which a Uop is dispatched on port 2Cycles with pending L1 cache miss loads. Set AnyThread to count per coreUnit: uncore_cbox Filter on processor core initiated cacheable read requestsMisses in all TLB levels that cause a page walk of any page size from demand loadsCounts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800001llc_misses.pcie_non_snoop_readllc_references.pcie_partial_readfreq_band2_cycles %unc_p_freq_ge_2000mhz_cyclesCounts the number of cycles that the uncore was running at a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010008br_misp_exec.all_direct_near_callpartial_rat_stalls.mul_single_uopbr_misp_retired.near_callThis event counts the number of load micro-ops retiredCounts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000020offcore_response.demand_data_rd.l2_hit_this_tile_eCounts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.partial_reads.l2_hit_this_tile_sCounts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in S stateCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000080offcore_response.partial_writes.l2_hit_this_tile_foffcore_response.pf_l2_rfo.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_rfo.l2_hit_near_tileoffcore_response.any_read.l2_hit_near_tileCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400044offcore_response.any_data_rd.ddr_farCounts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080801000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800100Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_data_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600200umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800004Counts L2 code HW prefetches that accounts for responses from DDR (local and far)Counts L1 data HW prefetches that accounts for responses from DDR (local and far)recycleq.lockrecycleq.any_ldmcdram bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk unc_e_wpq_insertsumask=0x3,period=100003,edge=1,event=0x5l1d_prefetch.requestsumask=0x7,period=100000,event=0xf1L2 load missesmem_uncore_retired.local_dramOffcore L1 data cache writebacksumask=0x10,period=5,event=0xb,ldlat=0x4000Offcore requests satisfied by the IO, CSR, MMIO unitoffcore_response.any_request.remote_cache_dramoffcore_response.any_request.remote_cache_hitOffcore requests that HITM in a remote cacheoffcore_response.corewb.any_cache_dramOffcore writebacks to a remote cache or remote DRAMoffcore_response.data_in.local_cache_dramoffcore_response.demand_data.remote_cacheOffcore demand code reads satisfied by the LLC or local DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4780Offcore prefetch data requests satisfied by the LLCOffcore prefetch data reads satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x710offcore_response.pf_data_rd.local_cache_dramoffcore_response.pf_data_rd.remote_cacheoffcore_response.pf_ifetch.io_csr_mmiooffcore_response.pf_ifetch.remote_cache_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F70umask=0x20,period=200000,event=0x12128 bit SIMD integer arithmetic operationssimd_int_64.packed_logicalumask=0x1,period=200000,event=0xfdoffcore_response.any_data.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF811offcore_response.demand_ifetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF880offcore_response.pf_data.any_llc_missOffcore prefetch data reads satisfied by a remote DRAMrat_stalls.registersbr_inst_exec.directUnconditional branches executedRetired near call instructions (Precise Event)umask=0x4,period=2000000,event=0xc0Total cycles (Precise Event)load_hit_preLoad operations conflicting with software prefetchesumask=0x20,period=2000000,event=0xa2umask=0x8,period=2000000,event=0xd1Uops executed on any port (core count)Cycles no Uops issued on ports 0-4 (core count)umask=0x40,period=2000000,event=0xb1Cycles no Uops were issueduops_retired.macro_fuseddtlb_misses.stlb_hitumask=0x1,period=200000,event=0x85period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0080001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080048000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000108000Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are countedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200400004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0040001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040040004Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetchperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000020004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0044000001offcore_response.demand_data_rd.l3_miss.any_snoopCounts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)memory_disambiguation.history_resetCycles total of 4 uops are executed on all ports and Reservation Station was not emptyCore crystal clock cycles when the thread is unhaltedCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5any=1,period=25003,umask=0x1,event=0x3cperiod=2000003,umask=0x3,event=0period=2000003,umask=0x1,event=0x87Increments whenever there is an update to the LBR arrayIpStore1000 * mem_load_retired.l3_miss / inst_retired.anyCounts any code reads (demand & prefetch) that miss L2offcore_response.any_code_rd.l2_miss.hitm_other_coreCounts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedThis event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the timeThis event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksCounts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040002offcore_response.pf_l2_data_rd.llc_miss.dramCounts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dramREQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMREQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5022REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIToffcore_response.demand_rfo.local_dram_and_remote_cache_hitREQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAMREQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAMCycles snoop code requests queuedMispredicted conditional retired branches (Precise Event)DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDECounts all demand & prefetch data reads that have any response typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0490Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0100offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdoffcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00010Counts all prefetch (that bring data to L2) RFOs that miss in the L3offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwdSummary;TmaL1uncore_chaumask=0x02,event=0x50uncore_iiounc_iio_data_req_of_cpu.mem_write.part0Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelinesCounts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHAunc_cha_llc_victims.total_eCounts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was inunc_cha_llc_victims.total_sumask=0x20,event=0x50Ingress (from CMS) Occupancy; IRQ. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data: Part 3fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc0Write request of 4 bytes made to IIO Part3 by the CPU. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_read.part1fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc1Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Total IRP occupancy of inbound read and write requests. Unit: uncore_irp unc_m2m_direct2core_takenevent=0x27Multi-socket cacheline Directory update from S to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)unc_upi_l1_power_cyclesCounts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the linkThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_e.hitm_other_coreoffcore_response.all_pf_data_rd.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00000107F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOPoffcore_response.all_reads.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04002007F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISSoffcore_response.all_reads.l3_hit_s.no_snoop_neededoffcore_response.all_reads.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_rfo.supplier_none.hitm_other_coreoffcore_response.all_rfo.supplier_none.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200004offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwdoffcore_response.demand_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.demand_rfo.supplier_none.no_snoop_neededoffcore_response.other.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800028000offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoopoffcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200010offcore_response.pf_l2_data_rd.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020020offcore_response.pf_l2_rfo.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwdoffcore_response.pf_l3_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_s.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000491ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000490ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoopocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_noneOCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000120ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_noneOCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000020ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_noneocr.pf_l3_data_rd.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000080ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.all_reads.l3_miss.hit_other_core_fwdoffcore_response.all_reads.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOPoffcore_response.demand_code_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_coreoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.other.l3_miss_local_dram.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoopoffcore_response.pf_l3_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSOCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDOCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_noneocr.all_pf_data_rd.supplier_none.hitm_other_coreocr.all_rfo.l3_hit.snoop_hit_with_fwdocr.all_rfo.l3_hit_s.hitm_other_coreocr.demand_code_rd.l3_hit_e.snoop_noneCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDEDCounts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.demand_data_rd.l3_hit.hitm_other_coreocr.demand_data_rd.l3_hit_e.snoop_missCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_f.hit_other_core_no_fwdocr.demand_rfo.pmm_hit_local_pmm.snoop_noneCounts any other requests  OCR.OTHER.L3_HIT_E.ANY_SNOOPCounts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_m.hit_other_core_fwdocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDEDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l2_rfo.supplier_none.hitm_other_coreocr.pf_l3_data_rd.any_responseCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDUNC_M_PMM_READ_LATENCYumask=0x1,event=0xeaumask=0x4,event=0xeaCounts all retired load instructions. This event accounts for SW prefetch instructions for loads  Supports address when precise (Precise event)cmask=1,period=1000003,umask=0x1,event=0x48Counts all microcode FP assistsCounts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)period=100003,umask=0x20,event=0x54cmask=2,period=1000003,umask=0x2,event=0xa3Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0020topdown.backend_bound_slotsTMA slots where no uops were being issued due to lack of back-end resourcesperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000002period=100003,umask=0x2,event=0xeCore cycles the allocator was stalled due to recovery from earlier clear event for this threadCounts core crystal clock cycles when the thread is unhaltedcmask=8,period=1000003,umask=0x8,event=0xa3uops_executed.cycles_ge_3Cycles when at least one PMH is busy with a page walk for code (instruction fetch) requestperiod=100003,umask=0x10,event=0x8Cache lines that are evicted by L2 cache when triggered by an L2 cache fillCounts the number of times a load got blocked due to false dependencies due to partial compare on address2LM Tag Check : Read Hit in Near Memory Cache. Unit: uncore_imc unc_m_rpq_occupancy_pch1unc_cha_tor_inserts.ia_hitTOR Inserts : All requests from iA Cores that Missed the LLC. Unit: uncore_cha umask=0xC001FF01,event=0x36TOR Occupancy : CRDs issued by iA Cores. Unit: uncore_cha umask=0xc8f3fe04,event=0x36unc_cha_tor_inserts.io_pcirdcurunc_cha_tor_inserts.ia_llcprefdataumask=0xCCD7FF01,event=0x35Four byte data request of the CPU : Card reading from DRAM. Unit: uncore_iio Data requested by the CPU : Core writing to Card's MMIO space. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_write.part7fc_mask=0x07,ch_mask=0x40,umask=0x80,event=0x84fc_mask=0x04,ch_mask=0x02,umask=0x03,event=0xc2umask=0x1C80,event=0x38Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3period=200003,umask=0x10,event=0x34period=200003,umask=0x1,event=0x34period=200003,umask=0x4,event=0xd1This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLESperiod=1000003,umask=0x20,event=0x74period=2000003,umask=0x4,event=0x49Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1)umask=0x02,event=0x8cl2_cache_req_stat.ls_rd_blk_csCore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2ex_ret_near_ret_mispredex_tagged_ibs_ops.ibs_tagged_ops_retdram_channel_data_controller_6Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory typels_stlfls_l1_d_tlb_miss.tlb_reload_4k_l2_missL1 DTLB Reload of a page of 1G sizeOC Mode Switch. IC to OC mode switchl2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3L2 Cache Hits from L2 HWPFbp_l1_tlb_fetch_hit.if4kFloating Point Dispatch Faults. XMM fill faultls_ret_cpuidNumber of SMIs receivedLS MAB Allocates by Type. DC prefetcherDemand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's diels_refills_from_sys.ls_mabresp_lcl_l2umask=0xff,event=0x4bAll Op Cache accesses. Counts Op Cache micro-tag hit/miss eventsThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPSls_hw_pf_dc_fills.ext_cache_remoteFP_DISPATCHED_FPU_OPSDC_MICROARCHITECTURAL_LATE_CANCELDC_DISPATCHED_PREFETCH_INSTRUCTIONSDC_DCACHE_ACCESSES_BY_LOCKSPC_PROC_RETURNMEM_ACCESSAXI_WRITEL1_DCACHE_NEON_ACCESSRET_STACK_MISPREDICTEVENT_23HEVENT_2EHEVENT_3FHEVENT_49HEVENT_50HEVENT_55HEVENT_57HEVENT_65HEVENT_74HEVENT_8FHEVENT_B7HEVENT_C6HJAZELLE_BACKWARD_BRANCHSTREX_FAILEDDATA_EVICTIONISBPLE_REQUEST_COMPLETEDBUS_ACCESS_STL1D_CACHE_LDL1D_CACHE_STICACHE_WRITE_MISSICACHE_EVICTL2CACHE_SET_TAG_WRITEL2_ERR_CORRECTEDIC_BLOCKED_CYCLESFSB_FULL_STALLSLDQ_OVER_50_FULLOCP_ALL_REQUESTSVFPU_INSTR_WAIT_CYCLESL1_DATA_SNOOP_HITSDSS_INSTR_COMPLETEDLSU_ALIAS_VS_FSQ_WB0_WB1FP_LOAD_DOUBLE_COMPLETED_IN_LSULSU_COMPLETES_FP_STORE_SINGLEFPU_INSTR_COMPLETEDL3_CACHE_HITSINTERVENTIONINSTR_COMPLETED_WITH_ALL_THREADS_RUNNINGSNOOP_PUSHESFPU_DOUBLE_PUMPk8-bu-cpu-clk-unhaltedx87low-op-pos-1dram-controller-queue-bypassBERIINTEL_HASWELLINTEL_SKYLAKE_XEONtopic: %s
l3_request_g1.caching_l3_cache_accesses{"type": "closelog"}
%s, "version": "0x%08x", "arch": "0x%08x", "cpuid": "%s", "tsc_freq": "%jd", "sec": "%jd", "nsec": "%jd"}
%s, "pmcid": "0x%08x", "pid": "%d"}
%s, "pid": "%d", "start": "0x%016jx", "end": "0x%016jx"}
%s, "tid": "%d", "pid": "%d", "flags": "0x%08x", "tdname": "%s"}
v17v1GenuineIntel-6-3CGenuineIntel-6-25cpu_clk_unhalted.threaduops_executed.thread / ( cpu@uops_executed.core\,cmask\=1@ / 2) if #smt_on else uops_executed.cycles_ge_1_uop_execFraction of cycles spent in Kernel modeumask=0x22,period=200003,event=0x24This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are countedlongest_lat_cache.referenceoffcore_requests.demand_data_rdRetired load uops misses in L1 cache as data sources. Uses PEBS  Supports address when precise (Precise event)umask=0x8,period=200003,event=0xf0l2_lines_in.iumask=0x2,period=100003,event=0xf1umask=0x20,period=2000003,event=0xc7umask=0x4,period=100003,event=0xcaidq.mite_uopsidq.ms_dsb_occurumask=0x2,period=200003,event=0x80umask=0x1,period=2000003,event=0xc8Number of times a disallowed operation caused an HLE abortThis event counts loads with latency value being above four  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_32Loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=1009,event=0xcd,ldlat=0x80Loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=2000003,event=0xeThis event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current threadmove_elimination.simd_not_eliminatedumask=0x84,period=200003,event=0x88This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirectsThis event counts taken speculative and retired mispredicted indirect branches that have a return mnemonicumask=0xc1,period=200003,event=0x89uops_dispatched_port.port_1This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2Cycles per thread when uops are executed in port 6Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired eventAll (macro) branch instructions retiredumask=0x10,period=400009,event=0xc4br_inst_retired.far_branchbr_misp_retired.all_branches_pebsbaclears.anyllc_misses.data_readLLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.pcie_ns_partial_writeM line forwarded from remote cache along with writeback to memory. Unit: uncore_ha (unc_m_power_critical_throttle_cycles / unc_m_dclockticks) * 100.event=0x4dtlb_load_misses.stlb_hitumask=0x60,period=2000003,event=0x8This category represents fraction of slots wasted due to incorrect speculationsInstructions Per Cycle (per Logical Processor)FLOPc_SMTDRAM_BW_UseThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Spec update: BDM100.  Supports address when precise (Precise event)offcore_response.demand_code_rd.supplier_none.snoop_missoffcore_response.pf_l2_rfo.l3_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0080offcore_response.pf_l3_rfo.supplier_none.snoop_hitmoffcore_response.pf_l3_rfo.supplier_none.any_snoopoffcore_response.pf_l3_code_rd.supplier_none.snoop_noneoffcore_response.other.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0090offcore_response.all_pf_code_rd.l3_hit.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020091Counts all demand & prefetch RFOs have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0122Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementumask=0x4,period=2000003,cmask=1,event=0x79offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000010offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwdoffcore_response.pf_l3_data_rd.l3_miss.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000200offcore_response.other.supplier_none.snoop_non_dramoffcore_response.other.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004008000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C008000offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_noneoffcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000090offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dramoffcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitmoffcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dramoffcore_response.all_data_rd.l3_miss_local_dram.snoop_noneoffcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000091Unit: uncore_cbox L3 Lookup read request that access cache and found line in any MESI-stateumask=0x16,event=0x34L3 Lookup read request that access cache and found line in E or S-stateuncore_arbTotal number of Core outgoing entries allocated. Accounts for Coherent and non-coherent trafficunc_arb_coh_trk_requests.allMemory_LatRetired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)offcore_response.all_requests.llc_hit.any_responseoffcore_response.all_reads.llc_hit.hitm_other_coreCounts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cacheCounts all demand & prefetch RFOs miss in the L3qpi_ctl_bandwidth_txl2_ld.self.any.i_stateumask=0x41,period=200000,event=0x2al2_lock.self.mesiumask=0x74,period=200000,event=0x2eRejected L2 cache requestsl2_reject_busq.self.demand.m_stateumask=0x40,period=200000,event=0x32umask=0xa1,period=2000000,event=0x40umask=0x89,period=200000,event=0x5misalign_mem_ref.st_bubbleumask=0x8f,period=200000,event=0x7umask=0x40,period=200000,event=0x60bus_trans_ifetch.all_agentsInstruction-fetch bus transactionsumask=0x8,period=200000,event=0x77cycles_int_masked.cycles_int_pending_and_maskedMultiply operations executedumask=0x1,period=2000000,event=0x14event=0x0,umask=0x03page_walks.i_side_cyclesCounts load uops retired that hit the L1 data cache  Supports address when precise (Must be precise)Counts load uops retired that miss in the L2 cache  Supports address when precise (Must be precise)umask=0x20,period=200003,event=0xd1umask=0x40,period=200003,event=0xd1umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003010Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time.  The forward might occur subsequently when the data is available (Must be precise)umask=0x4,period=200003,event=0x3umask=0x0,period=200003,event=0x9cmachine_clears.allRetired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise)umask=0xfb,period=200003,event=0xc5umask=0x10,period=200003,event=0xe6Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010008Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_neededCounts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.any_responseCounts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.any_rfo.any_responseoffcore_response.any_read.outstandingPage walk completed due to an instruction fetch in a 4K pageumask=0x4,period=2000003,event=0x85Cycles in which the L1D is lockedoffcore_response.all_rfo.l3_hit.hitm_other_coreCounts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00020This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-endCycles per core when uops are executed in port 5Cycles which a uop is dispatched on port 7 in this threadCycles where at least 2 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31Completed page walks due to misses in ITLB 2M/4M page entriesCompleted page walks in ITLB of any page sizeNumber of ITLB page walker loads that hit in the L3  Spec update: HSD25Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)offcore_response.demand_data_rd.llc_hit.hitm_other_corehsx metricsumask=0x40,period=200003,event=0x24umask=0xc0,period=200003,event=0x24Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycleAll retired store uops. (Precise Event)Retired load uops which data sources were hits in LLC without snoops required (Precise event)Counts all demand rfo'sumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010004simd_fp_256.packed_doubleoffcore_response.all_code_rd.llc_miss.dramNumber of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)Cycles per core when uops are dispatched to port 5umask=0x80,event=0x81Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x803c8000Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean responseivt metricsCounts all demand & prefetch code reads that miss the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f800244umask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004003f7umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc003f7offcore_response.demand_code_rd.llc_miss.remote_dramoffcore_response.demand_code_rd.llc_miss.remote_hitmCounts demand data reads that miss the LLC  and the data returned from remote dramunc_c_tor_occupancy.miss_localunc_m_act_count.rdunc_p_freq_band2_cyclesAll retired load uops (Precise event)Loads with latency value being above 4  (Must be precise)Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for Loads delayed due to SB blocks, preceding store operations with known addresses but unknown dataumask=0x3,event=0x36Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple timesl2_requests.referenceCounts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeCounts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_rfo.l2_hit_far_tile_mCounts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_request.l2_hit_far_tile_e_foffcore_response.uc_code_reads.l2_hit_near_tile_mCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any responseoffcore_response.partial_reads.l2_hit_far_tile_mCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for any responseoffcore_response.pf_l2_rfo.l2_hit_far_tile_moffcore_response.pf_l2_rfo.l2_hit_near_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400001offcore_response.any_data_rd.l2_hit_this_tile_moffcore_response.pf_l1_data_rd.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004002000Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S stateCounts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F stateCounts any Read request  that accounts for responses which hit its own tile's L2 with data in F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateCounts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_data_rd.l2_hit_far_tileoffcore_response.any_read.ddr_nearoffcore_response.any_request.mcdram_farCounts L1 data HW prefetches that accounts for data responses from MCDRAM LocalCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactionsumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000040offcore_response.pf_l2_rfo.non_dramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020020offcore_response.pf_l2_rfo.mcdram_nearoffcore_response.any_read.mcdramCounts any Read request  that accounts for responses from MCDRAM (local and far)offcore_response.uc_code_reads.ddrCounts the number of near relative CALL branch instructions retired (Precise event)Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken (Precise event)Counts the number of core cycles when no micro-ops are allocated and the ROB is fullno_alloc_cycles.allrecycleq.ld_block_st_forwardddr bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_imc uncore_edc_eclkl1d_cache_st.e_stateL1 data cache stores in S stateumask=0x4,period=100000,event=0x28All L2 transactionsumask=0x10,period=100000,event=0x27Instructions retired which contains a load (Precise Event)mem_load_retired.hit_lfbmem_load_retired.other_core_l2_hit_hitmoffcore_requests_sq_fullMemory instructions retired above 0 clocks (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF11Offcore data reads satisfied by the LLCoffcore_response.data_ifetch.remote_cache_hitOffcore demand data requests satisfied by any cache or DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x703Offcore demand data requests satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3801umask=0x1,period=100000,event=0xb7,offcore_rsp=0x801offcore_response.demand_rfo.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8002umask=0x1,period=100000,event=0xb7,offcore_rsp=0x280offcore_response.other.local_cacheoffcore_response.pf_data_rd.llc_hit_other_core_hitoffcore_response.prefetch.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3870X87 Floating poiint assists for invalid input value (Precise Event)Offcore data reads satisfied by a remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6004umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2040offcore_response.pf_rfo.any_llc_missbpu_clears.earlyScoreboard stall cyclesseg_rename_stallssq_full_stall_cyclesIndirect non call branches executedumask=0x30,period=20000,event=0x88br_misp_exec.condumask=0x4,period=2000000,event=0x87Reservation Station full stall cyclesuops_decoded.esp_foldingUops decoded by Microcode Sequenceruops_decoded.stall_cyclesuops_executed.core_active_cyclesumask=0x2,period=200000,event=0x85period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040080004Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001C0004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0080004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0100002Retired load instructions missed L1 cache as data sources  Supports address when precise (Precise event)any=1,cmask=1,period=2000003,umask=0x1,event=0x48period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040080001period=100003,umask=0x11,event=0xd0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200400001Retired instructions with at least 1 uncacheable load or lock  Supports address when precise (Precise event)period=200003,umask=0x21,event=0x24offcore_response.demand_data_rd.l3_hit_s.any_snoopoffcore_response.demand_code_rd.l3_hit_m.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040100004Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructionsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080004offcore_response.demand_code_rd.l3_hit_e.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080004offcore_response.demand_code_rd.l3_hit_s.snoop_missperiod=100007,umask=0x1,event=0xc6,frontend=0x408006Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event)period=200003,umask=0x1,event=0x83frontend_retired.stlb_missperiod=2000003,umask=0x8,event=0x79frontend_retired.latency_ge_2Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC408000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104008000Demand Data Read requests who miss L3 cachetx_mem.abort_capacityperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x20001C0002sw_prefetch_access.t0period=2000003,umask=0x10,event=0xa6Mispredicted direct and indirect near call instructions retired (Precise event)inst_retired.any / ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * cycles )HPC;Summarydtlb_store_misses.walk_activeCounts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultcmask=1,period=100003,umask=0x10,event=0x8This event counts the number of retire loads that experienced cache line boundary splits (Precise event)Counts DCU hardware prefetcher data read that have any response typeCounts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch RFOs that miss L2 with a snoop miss responseoffcore_response.demand_data_rd.l2_miss.snoop_missThis event counts all instruction fetches from the instruction cacheCounts the number of mispredicted JCC branch instructions retired (Precise event)Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event)This event counts the number of times that pipeline stalled due to FP operations needing assistsRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event)offcore_response.pf_l2_code_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400002snb metricsREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x50ffoffcore_response.demand_data.local_dram_and_remote_cache_hitoffcore_response.demand_data_rd.all_local_dram_and_remote_cache_hitREQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff40umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf808offcore_response.demand_data.other_local_dramREQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2050offcore_response.pf_data_rd.any_dram_and_remote_fwdSnoop code requestssnoopq_requests.datasnoopq_requests_outstanding.codeCycles snoop data requests queuedDTLB miss large page walksumask=0x4,period=2000000,event=0x49umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5811offcore_response.all_pf_data_rd.l3_hit.hitm_other_coreOFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0120Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0001Counts all demand data writes (RFOs) that have any response typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010100offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00122offcore_response.pf_l1d_and_sw.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00010Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dramidi_misc.wb_downgradeMemoryBWIoBW;SoC;Serverunc_m_wpq_occupancyfc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x83Core Cross Snoops Issued; Multiple Eviction. Unit: uncore_cha unc_cha_dir_update.torunc_cha_fast_asserted.horzumask=0x80,event=0x19Counts number of entries in the specified Ingress queue in each cycleumask=0x02,event=0x3dunc_cha_snoop_resp.rspsfwdCounts clockticks of the 1GHz trafiic controller clock in the IIO unitPCIe Completion Buffer Inserts of completions with data: Part 0unc_iio_comp_buf_occupancy.cmpd.part0Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc0unc_iio_data_req_by_cpu.peer_read.part2Read request for up to a 64 byte transaction is made by the CPU to IIO Part3. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busCounts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busCounts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busNumber of reads in which direct to core transaction were overridden. Unit: uncore_m2m event=0x28Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared)umask=0x2,event=0x38Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writesevent=0x56AD Ingress (from CMS) Queue Inserts. Unit: uncore_m2m uncore_m3upiCounts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyumask=0x97,event=0x2This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080490offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwdoffcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C07F7This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000807F7offcore_response.all_reads.l3_hit_f.any_snoopoffcore_response.all_reads.supplier_none.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800207F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100122offcore_response.all_rfo.pmm_hit_local_pmm.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOPThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400020This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwdoffcore_response.pf_l3_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020100OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_miss.hitm_other_coreocr.all_pf_data_rd.l3_miss.remote_hitmocr.all_pf_data_rd.l3_miss.snoop_missocr.all_pf_data_rd.l3_miss.snoop_noneocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC0007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss_local_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01100007F7ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000004ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_coreocr.demand_rfo.l3_miss.snoop_noneCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90008000ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l2_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000010ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000020ocr.pf_l3_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000100offcore_response.all_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISSoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.all_reads.l3_miss_local_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreoffcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_data_rd.l3_hit_e.hitm_other_coreOCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONEOCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOPocr.all_pf_data_rd.l3_hit_s.no_snoop_neededOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit.snoop_noneOCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit.any_snoopOCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONEOCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWDOCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_M.HITM_OTHER_COREOCR.ALL_READS.L3_HIT_M.SNOOP_MISSocr.all_reads.supplier_none.snoop_missOCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISSocr.all_rfo.l3_hit_f.hit_other_core_fwdOCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDOCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_e.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit.any_snoopocr.demand_data_rd.l3_hit_e.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOPocr.demand_data_rd.l3_hit_s.snoop_noneCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.other.l3_hit.hitm_other_coreCounts any other requests  OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDEDCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_f.snoop_noneocr.pf_l2_data_rd.l3_hit_e.no_snoop_neededocr.pf_l2_data_rd.l3_hit_e.snoop_noneCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOPocr.pf_l2_rfo.supplier_none.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOPocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwdRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event)Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending ) / ( 2 * cpu_clk_unhalted.distributed )Number of times an HLE execution aborted due to any reasons (multiple categories may count as one)Counts the number of times an RTM execution aborted due to incompatible memory typetx_mem.abort_capacity_readCounts the number of times we could not allocate Lock Bufferocr.other.dramCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.demand_rfo.dramCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.demand_rfo.l3_hit.anyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C2380Mispredicted indirect CALL instructions retired (Precise event)misc_retired.lbr_insertsTBD  Supports address when precise (Precise event)For every cycle, increments by the number of outstanding data read requests the core is waiting on.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestorRetired demand load instructions which missed L3 but serviced from local IXP memory as data sources  Supports address when precise (Precise event)umask=0x04,event=0x2Number of DRAM Refreshes Issued. Unit: uncore_imc umask=0x02,event=0x45umask=0x0c,event=0x50Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_crdTOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_rfo_prefumask=0xC807FF01,event=0x35TOR Inserts : RFOs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_crdumask=0xCC57FF01,event=0x35unc_cha_tor_occupancy.ia_miss_drd_pmmData requested of the CPU : CmpD - device sending completion to CPU request. Unit: uncore_iio Data requested by the CPU : Core reporting completion of Card read from Core DRAM. Unit: uncore_iio fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0x84FAF allocation -- sent to ADQ. Unit: uncore_irp Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response typemachine_clears.anyCounts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assistClockticks of the integrated IO (IIO) traffic controllerperiod=200003,umask=0x10,event=0xe6This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKECounts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows (Precise event)period=2000003,umask=0x1,event=0x4fumask=0x80,event=0x61Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2umask=0x07,event=0x64umask=0xf0,event=0fp_retx87_fp_ops.allThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-StoresLS MAB allocates by type - storesL1 DTLB Miss or Reload off all sizesls_l1_d_tlb_miss.tlb_reload_1g_l2_hitumask=0x03,event=0x46sse_avx_stallsremote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15SSE bottom-executing uOps retired. The number of serializing Ops retiredevent=0x37L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLBL1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLBSoftware Prefetch Data Cache Fills by Data Source. From another cache (home node remote)ls_hw_pf_dc_fill.ls_mabresp_lcl_dramevent=0x78L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting. Unit: uncore_l3pmc event=0xccls_mab_alloc.hardware_prefetcher_allocationsHardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entryumask=0x04,event=0x5aCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semanticsIC_MICROARCHITECTURAL_RESYNC_BY_SNOOPIC_RETURN_STACK_OVERFLOWL1_CACHE_PAGECOL_ALIASEVENT_03HEVENT_08HEVENT_09HEVENT_0DHEVENT_1CHEVENT_5BHEVENT_6CHEVENT_85HEVENT_BFHEVENT_CEHEVENT_F3HEVENT_FBHCOHERENT_LINEFILL_HITCINSTR_MAIN_TLB_MISS_STALLL1D_CACHEL2D_CACHE_REFILL_STLD_SPECBUS_ACCESS_NOT_SHAREDL1D_TLB_WRICACHE_READ_HITDCACHE_READ_MISSEJTAG_ITRIGGERWBB_QUARTER_TO_HALFCYCLESJR_31_MISPREDICTIONSNO_INSN_CYCLESJWBUFLDL1_DATA_TOTAL_MISSESFALL_THROUGH_BRANCHES_PROCESSEDBRANCH_UNIT_STALL_ON_CTR_DEPENDENCYDSSALL_INSTR_COMPLETEDSUCCESSFUL_STWCXL2_CACHE_CASTOUTSL2SQ_FULL_CYCLESBR_MARKED_INSTR_FINISHMARKED_STORE_WITH_INTRGROUP_DISPATCH_REJECTINSTR_COMPLETED_RUNNINGTOUCHES_TRANSLATEDCACHEOPS_TRANSLATEDLOAD_MISS_DLFB_FULL_CYCLESL2MMU_MISSESL2_CACHE_DIRTY_REDUNDANT_UPDATESFPU_PIPE_SYNC_STALLSSTWCX_FAILURESbranch-mispredictscycles-in-requestread-to-write-turnaroundnopUSERARMV7_CORTEX_A8SSps->ps_state != PL_STATE_ERRORERROR: unrecognized event type: %d
{"type": "initialize"v5coreTotal number of retired InstructionsMLPGiga Floating Point Operations Per SecondC2_Pkg_Residencyl2_rqsts.rfo_hitl2_demand_rqsts.wb_hitDemand Data Read requests sent to uncoremem_uops_retired.all_stores(null)L2 fill requests that access L2 cacheUops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathThis event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accessesumask=0x1,cmask=4,period=2000003,event=0x9cUnfriendly TSX abort triggered by  a vzeroupper instructionumask=0x1,period=503,event=0xcd,ldlat=0x100Unhalted core cycles when the thread is in ring 0This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliasedNumber of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-archThis event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetchCycles when Reservation Station (RS) is empty for the threadSpeculative and retired macro-conditional branchesumask=0xc2,period=200003,event=0x88umask=0x41,period=200003,event=0x89Cycles per core when uops are dispatched to port 3Counts number of cycles no uops were dispatched to be executed on this threaduops_executed.coreumask=0x2,cmask=2,period=2000003,event=0xb1Cycles at least 4 micro-op is executed from any thread on physical corellc_misses.code_llc_prefetchumask=0x1,event=0x35,filter_opc=0x18cunc_h_snoop_resp.rspsfwdCycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc Cycles all ranks are in critical thermal throttle. Unit: uncore_imc (unc_m_power_self_refresh / unc_m_dclockticks) * 100.uncore_pcuCounts the number of cycles when temperature is the upper limit on frequency. Unit: uncore_pcu Number of DTLB page walker hits in the L1+FB  Spec update: BDM69, BDM98BpTBinst_retired.any / br_inst_retired.all_branchesIpMispredictPage_Walks_Utilization_SMT1000 * mem_load_uops_retired.l2_miss / inst_retired.anyRetired load uops with locked access. (Precise Event - PEBS)  Spec update: BDM35.  Supports address when precise (Precise event)offcore_response.demand_rfo.any_responseoffcore_response.pf_l2_data_rd.any_responseoffcore_response.pf_l2_rfo.supplier_none.snoop_noneCounts all prefetch (that bring data to LLC only) code reads have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0080Counts prefetch (that bring data to LLC only) code readsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010091offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwdoffcore_response.all_data_rd.l3_hit.any_snoopoffcore_response.demand_data_rd.l3_miss.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000010offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwdoffcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000090offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoopoffcore_response.all_data_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000091offcore_response.all_rfo.l3_miss_local_dram.any_snoopThis event counts resource-related stall cyclesumask=0x6,period=2000003,cmask=6,event=0xa3umask=0x48,event=0x22unc_arb_trk_requests.allbdx metricsAverage number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetchesRetired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: BDE70 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8FFFumask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC007F7Counts all demand & prefetch code reads miss the L3 and the data is returned from local dramCounts all demand & prefetch data reads miss in the L3This event counts the number of retirement slots used (Precise event)8Bytes(unc_m_power_critical_throttle_cycles / unc_m_clockticks) * 100.L2 cache lines evictedModified lines evicted from the L2 cacheumask=0x42,period=200000,event=0x28l2_ld.self.demand.m_stateumask=0x58,period=200000,event=0x29l2_rqsts.self.demand.e_statel2_rqsts.self.demand.s_stateumask=0x72,period=200000,event=0x30l2_reject_busq.self.demand.e_statel2_reject_busq.self.prefetch.i_stateFXCH uops executedumask=0x10,period=2000000,event=0xc7Retired computational Streaming SIMD Extensions (SSE) packed-single instructionsStore splitsumask=0x0,period=200000,event=0x3abus_drdy_clocks.this_agentumask=0xe0,period=200000,event=0x7eCycles the divider is busyumask=0x4,period=200000,event=0x89br_missp_type_retired.ind_callbr_inst_retired.mispred_takenumask=0xc,period=2000000,event=0xc4umask=0x41,period=200003,event=0x2eumask=0x4f,period=200003,event=0x2eumask=0x80,period=200003,event=0xd1umask=0x1,period=100007,event=0xb7,offcore_rsp=0x36000032b7offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_neededCounts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400004000Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cacheoffcore_response.demand_rfo.l2_miss.hitm_other_coreumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040002decode_restriction.predecode_wrongUops requested but not-delivered to the back-end per cycleumask=0xbf,period=200003,event=0xc4umask=0xfb,period=200003,event=0xc4umask=0x1,period=200003,event=0xe6Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013010Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Instructions retired - using Reduced Skid PEBS feature (Must be precise)umask=0x2,period=200003,event=0x8itlb_misses.walk_completed_1gbCounts STLB flushes.  The TLBs are flushed on instructions like INVLPG and MOV to CR3Counts the number of store RFO requests that hit the L2 cacheOffcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61All retired store uops. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30.  Supports address when precise (Precise event)This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis  Spec update: HSD135Cycles in which the L1D and L2 are locked, due to a UC lock or split lockNon-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetchCycles at least 1 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles no executable uops retired on core (Precise event)umask=0x24,event=0x22Number of DTLB page walker hits in Memory  Spec update: HSD25Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise.  Spec update: HSM30 (Precise event)offcore_response.pf_l2_code_rd.llc_hit.any_responsel2_store_lock_rqsts.missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0091offcore_response.demand_data_rd.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3004003f7Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or notCycles with pending memory loads. Set AnyThread to count per coreUnit: uncore_arb Number of requests allocated in Coherency Trackeritlb_misses.large_page_walk_completedoffcore_response.all_pf_data_rd.llc_hit.hitm_other_coreCounts all prefetch (that bring data to L2) code reads that hit in the LLCCounts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cacheCounts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereLLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode.data_read. Unit: uncore_cbox (unc_p_freq_band2_cycles / unc_p_clockticks) * 100.dtlb_load_misses.demand_ld_walk_completedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC20077Valid instructions written to IQ per cycleResource stalls due to Rob being full, FCSW, MXCSR and OTHERunc_c_tor_occupancy.miss_alloffcore_response.any_read.l2_hit_far_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000044offcore_response.any_request.l2_hit_far_tile_moffcore_response.pf_software.l2_hit_far_tile_moffcore_response.uc_code_reads.outstandingoffcore_response.partial_writes.l2_hit_far_tile_e_foffcore_response.partial_reads.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400020Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_request.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000040offcore_response.any_code_rd.l2_hit_this_tile_eCounts any Read request  that accounts for responses which hit its own tile's L2 with data in E stateCounts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_foffcore_response.partial_writes.l2_hit_near_tileCounts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_data_rd.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800403091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200070Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101001000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800020Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Localoffcore_response.demand_rfo.mcdramoffcore_response.demand_data_rd.ddrCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800200umask=0x8,period=200003,event=0x4Counts the number of load micro-ops retired that cause a DTLB miss  Supports address when precise (Precise event)cache_lock_cycles.l1d_l2All references to the L1 data cacheumask=0x4,period=2000000,event=0x40L1 data cache read in M stateumask=0x80,period=200000,event=0x26umask=0x20,period=200000,event=0x26l2_write.lock.hitumask=0xe0,period=100000,event=0x27umask=0x41,period=100000,event=0x2eLongest latency cache missmem_load_retired.llc_unshared_hitumask=0x10,period=100,event=0xb,ldlat=0x400umask=0x10,period=2000,event=0xb,ldlat=0x40offcore_response.any_data.any_cache_dramoffcore_response.any_ifetch.remote_cache_hitoffcore_response.data_ifetch.io_csr_mmiooffcore_response.demand_data.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1003Offcore demand data reads satisfied by a remote cache or remote DRAMoffcore_response.demand_ifetch.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4704umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1804Offcore demand RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.demand_rfo.remote_cache_dramoffcore_response.other.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1080umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3830Offcore prefetch data reads satisfied by the LLCOffcore prefetch requests that HITM in a remote cacheMMX UopsTransitions from MMX to Floating Point instructionssimd_int_128.packsimd_int_128.packed_logicalInstructions decodedoffcore_response.corewb.any_dramOffcore demand data requests satisfied by any DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2004umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF802umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6080Offcore prefetch data requests that missed the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4030offcore_response.prefetch.any_llc_missL1I instruction fetch stall cyclesl1i.hitsLoads dispatched that bypass the MOBbr_inst_exec.anyConditional branch instructions executedild_stall.regenLoad buffer stall cyclesresource_stalls.mxcsrumask=0x4,period=200000,event=0xc7Cycles no Uops are decodedumask=0x3f,any=1,period=2000000,cmask=1,event=0xb1Cycles no Uops were issued on any threadCycles Uops were issued on either threadUops retired (Precise Event)umask=0x10,period=2000000,event=0x8DTLB second level hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00401C0002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400001offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitmCounts all demand data writes (RFOs)have any response typeoffcore_response.other.l3_hit_m.snoop_noneoffcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwdcmask=1,period=2000003,umask=0x2,event=0x60offcore_response.demand_rfo.supplier_none.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010001offcore_response.demand_code_rd.l3_hit_m.snoop_missCounts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are countedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040108000period=100003,umask=0x8,event=0xb0period=200003,umask=0xe2,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020002Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4period=100007,umask=0x1,event=0xc6,frontend=0x401006cmask=1,period=2000003,umask=0x30,event=0x79frontend_retired.latency_ge_2_bubbles_ge_2Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000080002offcore_response.demand_data_rd.l3_miss.snoop_hitmperiod=2003,umask=0x1,event=0xcd,ldlat=0x40period=2000003,umask=0x10,event=0x60hle_retired.aborted_unfriendlyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000400002period=2000003,umask=0x2,event=0xc8offcore_response.demand_rfo.l3_hit_m.snoop_non_dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC400001period=2000003,umask=0x2,event=0x54Number of times we entered an RTM region. Does not count nested transactionsperiod=203,umask=0x1,event=0xcbCounts the number of x87 uops dispatchedperiod=25003,umask=0x1,event=0x3cperiod=2000003,umask=0x40,event=0xa1This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: SKL091 (Must be precise)period=100003,umask=0x1,event=0x49Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in SkylakeThis event counts the number of load ops retired that miss in the L2 (Precise event)Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts any request that have any response typeCounts code reads generated by L2 prefetchers that miss L2 with a snoop miss responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000020Counts RFO requests generated by L2 prefetchers that miss L2offcore_response.demand_code_rd.l2_miss.snoop_missThis event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstandingJCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branchRetired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event)Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts all demand rfo's umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400120Offcore demand code read requestsCycles offcore demand data read busyREQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITMREQUEST = CORE_WB and RESPONSE = ANY_LOCATIONREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHEumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5001REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_RFO and RESPONSE = IO_CSR_MMIOoffcore_response.prefetch.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f70REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDoffcore_response.corewb.any_dram_and_remote_fwdoffcore_response.data_ifetch.any_dram_and_remote_fwdREQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAMoffcore_response.pf_data.any_dram_and_remote_fwdREQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISSSnoop data requestsSnoop invalidate requestsoffcore_requests.uncached_memumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2744umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6050inv=1,umask=0x3f,period=2000000,cmask=1,edge=1,event=0xb1Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts all prefetch (that bring data to L2) RFOs that have any response typeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0100Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cacheCounts demand data reads that miss the L3 and the data is returned from remote dramCounts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cacheCounts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dramoffcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=200003,umask=0x18,event=0x28Core cycles the core was throttled due to a pending power level requestunc_m_cas_count.rd_underfillumask=0x2,event=0x4umask=0x01,event=0x50read requests from local home agent. Unit: uncore_cha write requests from home agent. Unit: uncore_cha fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83PCI Express bandwidth reading at IIO, part 0. Unit: uncore_iio LLC_MISSES.PCIE_READPCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part0 +unc_iio_data_req_of_cpu.mem_write.part1 +unc_iio_data_req_of_cpu.mem_write.part2 +unc_iio_data_req_of_cpu.mem_write.part3umask=0x42,event=0x33unc_cha_rxc_occupancy.irqunc_cha_snoop_resp.rsp_fwd_wbunc_cha_snoop_resp.rsp_wbwbunc_iio_comp_buf_occupancy.cmpd.part3fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc0Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x84unc_i_faf_insertsevent=0x19umask=0x2,event=0x22Messages sent direct to the Intel UPI. Unit: uncore_m2m Multi-socket cacheline Directory update from A to I. Unit: uncore_m2m Multi-socket cacheline Directory update from I to A. Unit: uncore_m2m unc_m2m_txc_bl_inserts.allFLITs received which bypassed the Slot0 Receive Buffer. Unit: uncore_upi ll Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode. Unit: uncore_upi ll period=100007,umask=0x10,event=0xd3offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080120offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_reads.pmm_hit_local_pmm.any_snoopoffcore_response.all_reads.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_hit_f.hitm_other_coreoffcore_response.demand_code_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit_f.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040001offcore_response.demand_data_rd.supplier_none.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040002offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwdoffcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwdoffcore_response.demand_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000208000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONEoffcore_response.other.pmm_hit_local_pmm.any_snoopoffcore_response.other.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_f.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080010offcore_response.pf_l2_data_rd.l3_hit_m.any_snoopoffcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020010offcore_response.pf_l2_rfo.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200020This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdOCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08040007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00840007F7ocr.all_reads.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000122ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwdOCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONEocr.demand_rfo.l3_miss_local_dram.any_snoopCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_coreocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_neededCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000100This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwdoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_missoffcore_response.all_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwdOCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_COREOCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONEocr.all_pf_rfo.l3_hit.hit_other_core_fwdocr.all_pf_rfo.l3_hit.hit_other_core_no_fwdocr.all_pf_rfo.l3_hit.snoop_missOCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONEocr.all_pf_rfo.supplier_none.snoop_missocr.all_reads.l3_hit.hit_other_core_fwdOCR.ALL_READS.L3_HIT_E.SNOOP_NONEOCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDOCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDOCR.ALL_RFO.L3_HIT_M.SNOOP_MISSOCR.ALL_RFO.L3_HIT_S.SNOOP_MISSocr.demand_code_rd.l3_hit.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.demand_code_rd.supplier_none.snoop_missCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORECounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit.hitm_other_coreocr.demand_rfo.l3_hit_f.any_snoopocr.demand_rfo.l3_hit_m.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_COREocr.demand_rfo.pmm_hit_local_pmm.snoop_not_neededocr.demand_rfo.supplier_none.snoop_noneCounts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_s.hit_other_core_no_fwdocr.other.supplier_none.hit_other_core_fwdocr.pf_l1d_and_sw.l3_hit.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_m.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOPCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISSocr.pf_l2_data_rd.l3_hit_e.any_snoopocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwdocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwdocr.pf_l2_rfo.l3_hit.snoop_noneocr.pf_l2_rfo.l3_hit_f.snoop_missCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_f.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORECounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDumask=0x02,event=0x2cDirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m l1d_pend_miss.fb_full_periodsCounts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementidq.mite_cycles_okcmask=5,period=1000003,umask=0x1,event=0x9c( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single ) / cpu_clk_unhalted.distributedperiod=100003,umask=0x20,event=0xc9Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)ocr.hwpf_l2_data_rd.dramocr.demand_data_rd.l3_hit.snoop_sentCounts demand data reads that hit a cacheline in the L3 where a snoop was sentCounts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sentuops_dispatched.port_2_3Cycles where the Store Buffer was full and no loads caused an execution stallresource_stalls.scoreboardcmask=1,period=1000003,umask=0x1,event=0xa3Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)Cycles when at least one PMH is busy with a page walk for a storeperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x8003C0001( 1000000000 * ( unc_cha_tor_occupancy.ia_miss_drd_pmm / unc_cha_tor_inserts.ia_miss_drd_pmm ) / cha_0@event\=0x0@ )umask=0x0B,event=0x1DRAM Activate Count : All Activates. Unit: uncore_imc PMM Commands : Underfill reads. Unit: uncore_imc umask=0x01,event=0xe4Local read requests that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores that Hit the LLC. Unit: uncore_cha TOR Inserts : CRds issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : All requests from IO Devices. Unit: uncore_cha umask=0xC001FF04,event=0x36unc_cha_tor_inserts.ia_hit_rfo_prefunc_cha_tor_inserts.io_hit_itomumask=0xC817FF01,event=0x36unc_cha_tor_inserts.ia_miss_drd_pref_localumask=0xc867fe01,event=0x35TOR Occupancy : PCIRdCurs issued by IO Devices. Unit: uncore_cha unc_iio_txn_req_of_cpu.mem_write.part6fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0x84unc_i_coherent_ops.wbmtoiCounts the number of load uops retired that miss in the level 1 data cache  Supports address when precise (Precise event)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event (Precise event)Clockticks in the UBOX using a dedicated 48-bit Fixed CounterCounts the total number of BACLEARSperiod=200003,umask=0x3,event=0x80period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2104000002Counts the total number of BTCLEARSbus_lock.allCounts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basisCounts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) missesCounts the number of page walks due to stores that miss the PDE (Page Directory Entry) cacheInstruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ emptyAll L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidatesumask=0xf6,event=0x64Other L3 Miss Request Types. Unit: uncore_l3pmc umask=0x01,event=0x6The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4umask=0x02,event=0x887Double precision divide/square root FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPSfp_num_mov_elim_scal_op.optimizedx87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bitsx87 bottom-executing uOps retiredSSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bitsumask=0x02,event=0x46Misaligned loadsumask=0x01,event=0x28al2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3L2 Cache Misses from L1 Data Cache Missesumask=0x03,event=0xaafp_disp_faults.ymm_spill_faultls_st_commit_cancel2.st_commit_cancel_wcb_fullls_refills_from_sys.ls_mabresp_rmt_cacheL1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLBCycles where the Micro-Op Queue is emptyde_dis_dispatch_token_stalls1.fp_sch_rsrc_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStallbp_l1_tlb_miss_l2_tlb_miss.coalesced_4kRetired Indirect Branch Instructions. The number of indirect branches retiredls_dmnd_fills_from_sys.mem_io_localAny Data Cache Fills by Data Source. From cache of different CCX in same nodeSoftware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different NodeHardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same nodeumask=0xff,event=0x44INSTR_RETIRED_ANYDC_COPYBACKL1_ICACHE_ACCESSCYCLES_STALLED_NEON_FULLQEVENT_2CHEVENT_61HEVENT_7CHEVENT_97HEVENT_CBHEVENT_D1HEVENT_D8HEVENT_DFHEVENT_F6HPREDICTABLE_FUNCTION_RETURNBR_IMMED_RETIREDL1D_CACHE_REFILL_STBR_RETIREDL2_WRITEBACKALU_EMPTY_CYCLESAGEN_BUBBLE_CYCLESUNCACHED_STORE_INSNSFAILED_SC_INSNSMISPREDICTION_STALLSVIU1_INSTR_COMPLETEDFP_LOAD_INSTR_COMPLETED_IN_LSUVTQ_LINE_FETCH_MISSL3_STORE_HITSEXTERNAL_INTERVENTIONSBUS_WRITES_NOT_RETRIEDPREFETCH_ENGINE_COLLISION_VS_STOREGROUP_MARKED_IDUMARKED_GROUP_ISSUEDADDERPART2_MISALIGNED_CACHE_ACCESS_CYCLESSYSCALL_TRAP_INTRSTASH_REQUESTSL2_CACHE_DATA_ACCESSESL2_CACHE_INSTR_ALLOCATIONSdc-missesIAPINTEL_IVYBRIDGEpmclog_get_event%s, "pid": "%d"}
%s, "userdata": "0x%08x"}
GenuineIntel-6-5CILP( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7*(dtlb_store_misses.walk_completed+dtlb_load_misses.walk_completed+itlb_misses.walk_completed)) / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cyclesGFLOPsC7 residency percent per packageumask=0x4f,period=100003,event=0x2el1d_pend_miss.fb_fullOffcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76lock_cycles.cache_lock_durationThis event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncoremem_uops_retired.stlb_miss_loadsmem_load_uops_retired.l2_missMiss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event)Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)sq_misc.split_lockThis event counts the number of split locks in the super queueNumber of transitions from SSE to AVX-256 when penalty applicable  Spec update: BDM30Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SIMD FP assists due to Output valuesThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEumask=0x80,period=2000003,event=0xc8umask=0x2,period=2000003,event=0xc9umask=0x1,period=101,event=0xcd,ldlat=0x200event=0x3cCycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clearint_misc.recovery_cycles_anycpu_clk_unhalted.thread_pThis event counts not taken macro-conditional branch instructionsumask=0xc4,period=200003,event=0x89This event counts both taken and not taken mispredicted indirect branches excluding calls and returnsCycles per thread when uops are executed in port 5umask=0x1,cmask=1,period=2000003,event=0xa3uops_executed.cycles_ge_2_uops_execumask=0x1,cmask=2,period=2000003,event=0xb1uops_executed.core_cycles_noneumask=0x1,period=2000003,event=0xc0Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired (Precise event)All mispredicted macro branch instructions retiredllc_misses.mmio_readunc_c_tor_occupancy.llc_data_readunc_m_pre_count.wrevent=0x80,occ_sel=3Load misses in all DTLB levels that cause page walks  Spec update: BDM69umask=0x1,period=100003,event=0x49itlb_misses.walk_completedThis category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU(( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / cyclesFLOPS_SMT64 * l2_lines_in.all / 1000000000 / duration_timeAverage per-core data fill bandwidth to the L3 cache [GB / sec]offcore_response.demand_data_rd.any_responseoffcore_response.demand_data_rd.supplier_none.snoop_not_neededoffcore_response.demand_data_rd.l3_hit.snoop_missoffcore_response.corewb.l3_hit.snoop_hit_no_fwdoffcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwdoffcore_response.pf_l3_rfo.l3_hit.snoop_hitmoffcore_response.all_pf_data_rd.supplier_none.snoop_noneoffcore_response.all_pf_code_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0091offcore_response.all_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0122Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementumask=0x1e,period=100003,cmask=1,event=0xcaRandomly selected loads with latency value being above 8  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000004offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0100offcore_response.pf_l3_rfo.l3_miss.snoop_noneoffcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000120umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000091This is a precise version (that is, uses PEBS) of the event that counts cycles without actually retired uopsCounts all not taken macro branch instructions retired. (Precise Event)Counts the number of far branch instructions retired.(Precise Event)  Spec update: BDW98umask=0x41,event=0x22Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor coreUnit: uncore_ncu This 48-bit fixed counter counts the UCLK cyclesRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwdCounts all demand & prefetch data reads miss the L3 and the data is returned from local dramoffcore_response.all_data_rd.llc_miss.any_responseThis event counts mispredicted return instructions retired (Precise event)uncore interconnectumask=0x2,event=0l2_ads.selfl2_lines_in.self.prefetchl2_data_rqsts.self.m_stateumask=0x54,period=200000,event=0x30umask=0x5f,period=200000,event=0x30FXCH uops retired (Must be precise)umask=0x84,period=2000000,event=0xb3Saturated arithmetic instructions retiredmisalign_mem_ref.splitNonzero segbase load 1 bubbleumask=0x86,period=200000,event=0x7Bus cycles when a LOCK signal is assertedbus_trans_wb.selfbus_trans_burst.all_agentsbus_hitm_drv.all_agentsCycles during which interrupts are pending and disableddiv.sumask=0x2,period=2000000,event=0x88Instructions retired (precise event) (Must be precise)Micro-ops retiredCycles no micro-ops retiredumask=0x0,period=200000,event=0xc5page_walks.d_side_cyclesmem_load_retired.dtlb_missoffcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.pf_l2_rfo.l2_hitoffcore_response.demand_code_rd.l2_hitReferences per ICache line. This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitecturemisalign_mem_ref.load_page_splitld_blocks.data_unknownCounts the number of integer divide uops retired (Must be precise)Retired taken branch instructions (Precise event capable) (Must be precise)br_inst_retired.returnCounts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystemCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000800Counts requests to the uncore subsystem hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003010Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredPage walk completed due to a demand load to a 1GB pageCounts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksAll requests that missed L2  Spec update: HSD78Counts any demand and L1 HW prefetch data load requests to L2  Spec update: HSD78This event counts all store uops retired. This is a precise event  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedNumber of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision bufferRandomly selected loads with latency value being above 8  Spec update: HSD76, HSD25, HSM26 (Must be precise)Counts all demand code reads miss the L3 and the data is returned from local dramNon-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetchExecution stalls due to L2 cache missesMisses in all TLB levels that cause a page walk of any page sizeumask=0x80,period=100003,event=0x8Store misses in all DTLB levels that cause completed page walksCompleted page walks due to misses in ITLB 4K page entriesRetired load uops with locked access  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event)Retired store uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops missed L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event)offcore_response.demand_data_rd.llc_miss.any_responseoffcore_response.pf_l2_rfo.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00040Counts the number of conditional branch instructions retired (Precise event)umask=0x20,period=200003,event=0x24Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncoreCounts all demand & prefetch RFOs that hit in the LLCother_assists.avx_storeIncrement each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cyclesCounts all demand & prefetch data reads that miss the LLC  and the data returned from dramoffcore_response.demand_code_rd.llc_miss.dramCycles which a Uop is dispatched on port 4umask=0x40,event=0x34Unit: uncore_cbox Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsCounts load operations that missed 1st level DTLB but hit the 2nd levelmem_load_uops_llc_miss_retired.remote_hitmoffcore_response.all_pf_data_rd.llc_hit.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_data_rd.llc_hit.no_snoop_neededrxl0p_power_cycles %unc_p_freq_band0_cycles(unc_p_freq_ge_3000mhz_cycles / unc_p_clockticks) * 100.Retired load uops that split across a cacheline boundary (Precise event)This event counts retired load uops that hit in the last-level (L3) cache without snoops requiredCycles when 1 or more uops were delivered to the by the front endjkt metricsThis event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excludedThis event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlersbr_misp_exec.taken_direct_near_callThis event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event)Uops dispatched from any threadoffcore_response.any_pf_l2.l2_hit_far_tile_e_fCounts any Read request  that accounts for any responseoffcore_response.any_rfo.l2_hit_far_tile_e_foffcore_response.demand_data_rd.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000004Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_code_rd.l2_hit_this_tile_moffcore_response.any_read.l2_hit_this_tile_eumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000200Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180200umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800181000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x18004032f7offcore_response.any_pf_l2.l2_hit_far_tileCounts all instruction fetches, including uncacheable fetchesCounts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080208000offcore_response.demand_code_rd.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800001offcore_response.bus_locks.ddrCounts Bus locks and split lock requests that accounts for responses from DDR (local and far)offcore_response.any_code_rd.ddruops_retired.packed_simdCounts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retireCounts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be includedl1d_cache_ld.mesiL1 data cache read in S stateumask=0x2,period=2000000,event=0x42L1D load lock accepted in fill bufferl2_data_rqsts.demand.m_stateumask=0x8,period=200000,event=0x26umask=0xf,period=200000,event=0x26L2 data demand requestsl2_rqsts.ifetchesl2_rqsts.ld_missL2 RFO hitsL2 fill transactionsL2 instruction fetch transactionsumask=0x20,period=100000,event=0x27mem_uncore_retired.remote_cache_local_home_hitmem_inst_retired.latency_above_threshold_32768offcore_response.any_data.remote_cache_hitmoffcore_response.any_ifetch.any_cache_dramOffcore code reads satisfied by the LLC and not found in a sibling coreOffcore code reads satisfied by the LLC or local DRAMOffcore code reads satisfied by a remote cacheoffcore_response.any_request.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8FFoffcore_response.corewb.any_locationumask=0x1,period=100000,event=0xb7,offcore_rsp=0x777offcore_response.data_ifetch.remote_cache_hitmOffcore request = all data, response = local cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3833All offcore demand data requestsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x103Offcore demand data requests that HITM in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1002umask=0x1,period=100000,event=0xb7,offcore_rsp=0x480umask=0x1,period=100000,event=0xb7,offcore_rsp=0x880umask=0x1,period=100000,event=0xb7,offcore_rsp=0x830umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1010offcore_response.pf_rfo.any_cache_dramoffcore_response.pf_rfo.any_locationoffcore_response.pf_rfo.remote_cacheOffcore prefetch requests satisfied by the IO, CSR, MMIO unitoffcore_response.prefetch.remote_cachefp_comp_ops_exe.mmxsimd_int_64.shuffle_moveoffcore_response.any_data.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2044umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF877offcore_response.data_in.local_dramoffcore_response.demand_data.any_llc_missOffcore demand data reads satisfied by the local DRAMOffcore demand RFO requests satisfied by any DRAMoffcore_response.demand_rfo.local_dramOffcore other requests that missed the LLCoffcore_response.pf_data.any_dramoffcore_response.pf_rfo.any_dramumask=0x2,period=2000000,event=0xe8All RAT stall cyclesBACLEAR asserted with bad target addressumask=0x8,period=20000,event=0x88Mispredicted near retired calls (Precise Event)inst_retired.total_cyclesssex_uops_retired.vector_integeruops_executed.core_stall_cycles_no_port5offcore_response.demand_rfo.supplier_none.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040028000mem_inst_retired.all_loadsmem_load_l3_hit_retired.xsnp_missperiod=100003,umask=0x42,event=0xd0cmask=1,period=2000003,umask=0x1,event=0x60period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400048000Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event)period=2000003,umask=0x1,event=0xabperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084008000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C408000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000004period=2000003,umask=0x10,event=0xc8period=2000003,umask=0x4,event=0x54period=2000003,umask=0x10,event=0x5dperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C400002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000040002offcore_response.demand_data_rd.l3_hit_m.snoop_non_dramDirect and indirect near call instructions retired  Spec update: SKL091 (Precise event)period=2000003,umask=0x8,event=0xa2Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not emptyInstructions per Load (lower number means higher occurrence rate)( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ) )inst_retired.any / ( br_inst_retired.far_branch / 2 )Page walk completed due to a demand data load to a 2M/4M pageCross core or cross module hitm (Precise event)This event counts the number of load ops retiredCounts any rfo reads (demand & prefetch) that have any response typeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680004800Counts data cacheline reads generated by L2 prefetchers that miss L2Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x3f,period=200003,event=0x86MSROM micro-ops retiredCycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty.  The divide instruction is one of the longest latency instructions in the machine.  Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructionsRetired load uops that miss the STLB. (Precise Event - PEBS) (Precise event)offcore_response.all_code_rd.llc_hit.snoop_missCounts all prefetch RFOs that miss the LLC  and the data returned from dramoffcore_response.pf_l2_code_rd.llc_miss.dramCounts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dramThis event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructionsumask=0x10,period=100000,event=0xb0umask=0x4,period=100000,event=0xb0Offcore demand RFO requestsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4ffREQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5010umask=0x1,period=100000,event=0xb7,offcore_rsp=0x20ffREQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x2,period=100000,event=0xb4Outstanding snoop code requestsCounts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0400offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwdOFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDCounts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000490offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdoffcore_response.all_rfo.l3_miss.remote_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800002offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00020offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdcha@event\=0x36\,umask\=0x21\,config\=0x40433@ / cha@event\=0x36\,umask\=0x21\,config\=0x40433\,thresh\=1@Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x0C,event=0x50Lines Victimized; Lines in M state. Unit: uncore_cha fc_mask=0x4,ch_mask=0x08,umask=0x03,event=0xc2Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit. Unit: uncore_iio fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc1Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busWrite request of up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x84unc_i_cache_total_occupancy.memumask=0x8,event=0x11Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socketCounts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400491This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040490This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_neededoffcore_response.all_pf_rfo.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020120This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801007F7offcore_response.all_reads.supplier_none.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000207F7This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200004This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040001offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C8000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C8000offcore_response.other.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_s.hit_other_core_no_fwdoffcore_response.pf_l1d_and_sw.l3_hit.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040020offcore_response.pf_l2_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.any_snoopoffcore_response.pf_l3_data_rd.l3_hit_e.snoop_missoffcore_response.pf_l3_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000491OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONEocr.all_data_rd.l3_miss_local_dram.hitm_other_coreOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000491ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000490OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss.remote_hitmOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOPocr.all_reads.l3_miss.hit_other_core_fwdocr.all_reads.l3_miss_local_dram.snoop_missocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwdocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_noneocr.demand_data_rd.l3_miss_local_dram.hitm_other_coreocr.other.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000400Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000010ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000010Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000080ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_missoffcore_response.all_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.all_reads.l3_miss.remote_hit_forwardoffcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_data_rd.l3_hit.hit_other_core_fwdOCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOPocr.all_data_rd.l3_hit_m.hitm_other_coreocr.all_pf_data_rd.any_responseocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwdOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONEocr.all_pf_rfo.l3_hit_e.any_snoopocr.all_pf_rfo.l3_hit_e.no_snoop_neededocr.all_pf_rfo.l3_hit_m.snoop_missocr.all_reads.l3_hit_e.hit_other_core_fwdocr.all_reads.l3_hit_e.no_snoop_neededOCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_f.hitm_other_coreocr.all_rfo.l3_hit_m.hit_other_core_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONECounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORECounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_m.snoop_missocr.demand_data_rd.l3_hit_s.any_snoopocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDCounts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.demand_rfo.l3_hit.any_snoopocr.demand_rfo.l3_hit_s.hit_other_core_fwdocr.other.l3_hit_e.hitm_other_coreCounts any other requests  OCR.OTHER.L3_HIT_E.HITM_OTHER_COREocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.supplier_none.snoop_noneocr.pf_l2_data_rd.l3_hit_f.hitm_other_coreocr.pf_l2_data_rd.l3_hit_m.snoop_noneCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit.no_snoop_neededocr.pf_l3_data_rd.l3_hit.any_snoopocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwdocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_noneTag Hit; Underfill Rd Hit from NearMem, Clean Lineperiod=1000003,umask=0x8,event=0x60Number of cycles a demand request has waited due to L1D due to lack of L2 resourcesSW prefetch requests that miss L2 cacheperiod=200003,umask=0x8,event=0xd1Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestperiod=100003,umask=0x2,event=0x32ocr.demand_code_rd.l3_hit.snoop_hit_no_fwdocr.streaming_wr.l3_hit.anyCounts return instructions retired (Precise event)cmask=12,period=1000003,umask=0xc,event=0xa3period=100003,umask=0x4,event=0x8unc_cha_tor_occupancy.ia_miss_drd / cha@event\=0x36\,umask\=0xc817fe01\,thresh\=1@DRAM Precharge commands. : Precharge due to write. Unit: uncore_imc unc_cha_tor_occupancy.iaumask=0xC807FE01,event=0x36unc_cha_tor_inserts.ia_miss_crd_prefTOR Inserts : RFO_Prefs issued by iA Cores. Unit: uncore_cha umask=0xCCD7FE01,event=0x35Clockticks of the integrated IO (IIO) traffic controller. Unit: uncore_iio unc_iio_txn_req_by_cpu.mem_read.part7fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0x84Counts the number of load uops retired. This event is Precise Event capable  Supports address when precise (Precise event)TOR Inserts; Code read prefetch from local IA that misses in the snoop filterTOR Inserts; RFO misses from local IA. Unit: uncore_cha Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written backperiod=200003,umask=0x1,event=0xe6Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguationperiod=1000003,umask=0x1,event=0x74period=200003,umask=0xf7,event=0xc4Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event)Counts the number of Extended Page Directory Pointer Entry missesCounts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cyclebp_l2_btb_correctInstruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressurel2_wcb_req.zero_byte_storel2_wcb_req.cl_zerol2_cache_req_stat.ic_dc_miss_in_l2L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 cachesCaching: L3 cache accesses. Unit: uncore_l3pmc event=0xc8MMX instructionsThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructionsTagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retiredTagged IBS Ops. Number of Ops tagged by IBS that retiredTagged IBS Ops. Number of Ops tagged by IBSumask=0x38,event=0x47fpu_pipe_assignment.total3fpu_pipe_assignment.total0umask=0x04,event=0x5umask=0x08,event=0x41L1 DTLB Reload of a page of 4K sizels_tablewalker.ic_type0Total Page Table Walks DC Type 0umask=0x08,event=0xafL1 DTLB Missesall_remote_links_outboundThe number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB pagefp_disp_faults.xmm_fill_faultumask=0x02,event=0x24Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lockls_ret_cl_flushumask=0x02,event=0x59All Instruction Cache Accesses. Counts various IC tag related hit and miss eventsOp Cache Hit. Counts Op Cache micro-tag hit/miss eventsThe number of CPUID instructions retiredls_any_fills_from_sys.mem_io_remoteHardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different NodeHardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same nodede_dis_cops_from_decoder.disp_op_type.any_fp_dispatchde_dis_dispatch_token_stalls1.load_queue_rsrc_stalld_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatchDC_ONE_BIT_ECC_ERRORIC_RETURN_STACK_HITNB_PROBE_RESULTCYCLES_STALLED_NEON_MRCPMUEXTIN1_EVTEVENT_26HEVENT_30HEVENT_33HEVENT_48HEVENT_51HEVENT_59HEVENT_6FHEVENT_83HEVENT_8BHEVENT_ADHEVENT_E5HCRYPTO_SPECEXC_UNDEFL2D_TLB_RDINSTDTLB_MISSDCACHE_EVICTRETURN_MISPREDJTLB_IMISSUNCACHED_LOADMFTC_COMPLETEDFSB_GT_HALFPREDICTED_JR_31UNCACHED_IFETCH_STALLSALCB_FULL_DR_STALLSDCACHE_MISSESJR_NON_31_INSNSCOREEXTEND_EVENTSOCP_WRITE_CACHEABLE_REQUESTSVSCR_SAT_SETBRANCHES_COMPLETEDLSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0LSU_STORE_QUEUE_INDEX_ALIASMFSPR_INSTR_COMPLETEDL1_DATA_CACHE_RELOADSGPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLDEXTERNAL_PUSHESBUS_TAS_FOR_READSBRANCH_MISPREDICTEDPREFETCHED_INSTRS_DISCARDEDLOAD_MISS_DLFB_FULLDATA_MMU_MISS_CYCLESIAC1S_DETECTEDDAC1S_DTECTEDmodifiedloadntammx-3dnowSOFTAMD_K7PPC_970LONGEST_LAT_CACHE.REFERENCEGenuineIntel-6-1CGenuineIntel-6-45GenuineIntel-6-46GenuineIntel-6-37GenuineIntel-6-2CCLKSPage_Walks_Utilization(cstate_pkg@c2\-residency@ / msr@tsc@) * 100l2_rqsts.l2_pf_hitl1d_pend_miss.pending_cyclesoffcore_requests_outstanding.demand_data_rdoffcore_requests.all_data_rdumask=0x1,period=100003,event=0xb7Retired load uops that miss the STLB. (Precise Event - PEBS)  Supports address when precise (Precise event)mem_load_uops_l3_hit_retired.xsnp_noneThis event counts Demand Data Read requests that access L2 cache, including rejectsThis event counts Read for Ownership (RFO) requests that access L2 cacheidq_uops_not_delivered.cycles_le_3_uop_deliv.coreumask=0x1,period=2000003,event=0x54tx_mem.abort_capacity_writeumask=0x8,period=2000003,event=0x54tx_exec.misc5umask=0x2,period=2000003,event=0xc8Number of times the TSX watchdog signaled an HLE abortCycles when L1 and L2 are locked due to UC or split lockNumber of flags-merge uops being allocated. Such uops considered perf sensitive
 added by GSR u-archcpu_clk_thread_unhalted.one_thread_activeumask=0x88,period=200003,event=0x88br_inst_exec.all_conditionalMispredicted indirect branches excluding calls and returnsuops_executed_port.port_1Cycles per core when uops are exectuted in port 5uops_executed_port.port_7_coreumask=0x8,period=2000003,event=0xa2This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front endExecution stalls while L2 cache miss demand load is outstandinglsd.cycles_4_uopsumask=0x1,period=2000003,event=0xb1br_inst_retired.conditionalumask=0x1,event=0x35,filter_opc=0x181read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69umask=0x1,period=100003,event=0x85umask=0x40,period=100003,event=0x85This category represents fraction of slots where the processor's Frontend undersupplies its Backend( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branchesumask=0xd0,period=200003,event=0x24This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Spec update: BDM100.  Supports address when precise (Precise event)offcore_response.demand_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0040offcore_response.other.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020240offcore_response.all_pf_code_rd.supplier_none.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0240offcore_response.all_data_rd.supplier_none.snoop_hitmumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020122umask=0x30,period=2000003,cmask=1,event=0x79umask=0x1,period=2000003,cmask=2,event=0x9cCounts randomly selected loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwdoffcore_response.demand_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000004offcore_response.corewb.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000008offcore_response.pf_l2_rfo.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000040offcore_response.pf_l2_code_rd.l3_miss.snoop_noneoffcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwdoffcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitmoffcore_response.pf_l3_code_rd.l3_miss.snoop_noneoffcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitmoffcore_response.all_pf_rfo.l3_miss.snoop_noneL3 Lookup any request that access cache and found line in M-stateL3 Lookup write request that access cache and found line in MESI-stateunc_arb_trk_requests.drd_directcbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182\,thresh\=1@offcore_response.all_reads.llc_miss.remote_hit_forwardCounts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_rfo.llc_miss.remote_hitml2_dbus_busy_rd.selfL2 cache demand requests from this core that missed the L2simd_inst_retired.packed_singlesimd_comp_inst_retired.packed_singleumask=0x3,period=200000,event=0x80This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQStore splits (Ar Retirement)misalign_mem_ref.rmw_bubbleRFO bus transactionsumask=0x40,period=200000,event=0x69umask=0x40,period=200000,event=0x6eReference cycles when core is not haltedAll indirect branches that are not callsumask=0x8,period=2000000,event=0x88Self-Modifying Code detectedpage_walks.i_side_walksumask=0x4,period=200000,event=0x82umask=0x1,period=100007,event=0xb7umask=0x82,period=200003,event=0xd0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000022Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040008Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other eventsThis event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issueCounts uops which retired (Must be precise)Retired near call instructions (Precise event capable) (Must be precise)br_inst_retired.ind_callRetired conditional branch instructions that were taken (Precise event capable) (Must be precise)umask=0x7e,period=200003,event=0xc5mem_uops_retired.dtlb_miss_loadsLoad uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x10,period=200003,event=0x8Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61offcore_response.demand_rfo.l3_hit.hitm_other_coreAny input SSE* FP Assist (Precise event)Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of deliveryNumber of uops delivered to IDQ from any pathCycles with less than 2 uops delivered by the front end  Spec update: HSD135( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / cyclesNumber of times an RTM execution startedoffcore_response.all_reads.l3_miss.any_responseoffcore_response.pf_l3_rfo.l3_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00004Counts all demand code reads miss in the L3This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttlingCycles with pending L1 data cache miss loads. Set Cmask=8 to count cycleAll (macro) branch instructions retired (Must be precise)Load misses in all DTLB levels that cause page walksLoad miss in all TLB levels causes a page walk that completes. (1G)Number of cache load STLB hits. No page walkumask=0x42,period=2000003,event=0xbcRetired load uops with L1 cache hits as data sources  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC007F7Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles  Supports address when precise (Precise event)umask=0x8,period=200003,event=0x27Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycleOffcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cyclesoffcore_response.all_code_rd.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000105B3umask=0x10,period=2000003,event=0x10umask=0x1,period=2000003,event=0xabumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400244Count XClk pulses when this thread is unhalted and the other is haltedCycles per core when uops are dispatched to port 0umask=0x30,period=2000003,event=0xa1uops_dispatched_port.port_4_coreNumber of instructions retired. General Counter   - architectural eventunc_cbo_xsnp_response.missumask=0x10,event=0x22unc_cbo_xsnp_response.xcore_filterUnit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to processor core memory requestUnit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to LLC evictionLLC lookup request that access cache and found line in E-stateUnit: uncore_cbox Filter on processor core initiated cacheable write requestsumask=0x80,event=0x34unc_arb_trk_occupancy.cycles_over_half_fullumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0010Counts prefetch (that bring data to LLC only) data reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc00244umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800004Counts all demand code reads that miss the LLC  and the data forwarded from remote cacheumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20040llc_misses.itom_write(unc_q_txl0p_power_cycles / unc_q_clockticks) * 100.umask=0x4,period=2000003,event=0x51umask=0x2,period=200003,event=0x28offcore_requests_outstanding.demand_data_rd_c6umask=0xe,period=2000003,event=0xa2Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Unit: uncore_cbox umask=0x20,period=200003,event=0x4Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_rfo.l2_hit_near_tile_moffcore_response.pf_software.outstandingumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400100Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000002offcore_response.uc_code_reads.l2_hit_this_tile_mCounts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M stateCounts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008001000Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateCounts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_code_rd.ddr_farCounts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_rfo.ddr_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800022offcore_response.pf_l1_data_rd.mcdram_faroffcore_response.pf_l1_data_rd.ddr_farCounts L1 data HW prefetches that accounts for data responses from DRAM Localoffcore_response.partial_reads.non_dramCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200002Counts Software Prefetches that accounts for responses from MCDRAM (local and far)Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far)Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800044Counts the number of mispredicted branch instructions retired (Precise event)This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assistsCounts the number of floating operations retired that required microcode assistsThis event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or trapsCounts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front endumask=0x2,period=2000000,event=0x40umask=0x1,period=2000000,event=0x42umask=0x1,period=100000,event=0x28l2_data_rqsts.demand.mesil2_data_rqsts.demand.s_stateL2 data demand loads in S stateAll L2 data prefetchesl2_rqsts.loadsl2_transactions.anyL2 demand lock RFOs in I state (misses)umask=0x2,period=40000,event=0xfLoad instructions retired that HIT modified data in sibling core (Precise Event)mem_uncore_retired.uncacheablestore_blocks.l1d_blockmem_inst_retired.latency_above_threshold_16384umask=0x10,period=50,event=0xb,ldlat=0x800Memory instructions retired above 2048 clocks (Precise Event)Offcore data reads satisfied by the LLC and not found in a sibling coreOffcore data reads that HITM in a remote cacheOffcore code reads satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x38FFOffcore RFO requests satisfied by any cache or DRAMOffcore RFO requests satisfied by the LLC and not found in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x722offcore_response.corewb.remote_cache_hitoffcore_response.data_ifetch.llc_hit_no_other_coreOffcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x403All offcore other requestsOffcore other requests satisfied by the LLC and HIT in a sibling coreOffcore other requests that HITM in a remote cacheOffcore prefetch data requests satisfied by the LLC and not found in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1830offcore_response.pf_data.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x410offcore_response.pf_ifetch.llc_hit_no_other_coreOffcore prefetch code reads satisfied by a remote cacheumask=0x2,period=20000,event=0xf7SIMD integer 64 bit logical operationsOffcore code reads satisfied by a remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xF833offcore_response.demand_data.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4002Offcore other requests satisfied by a remote DRAMoffcore_response.pf_data.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2070umask=0x4,period=2000000,event=0x80umask=0x1,period=2000000,event=0x80Large ITLB hitFalse dependencies due to partial address aliasingumask=0x8,period=2000000,event=0xd2lsd.activeumask=0x10,period=2000000,event=0xa2SIMD Packed-Single Uops retired (Precise Event)umask=0x2,period=200000,event=0x49period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400400002Counts all demand code readshave any response typeoffcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitmCounts the RFO (Read-for-Ownership) requests that miss L2 cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100048000offcore_response.other.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0020004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040040001Retired load instructions which data sources were hits in L3 without snoops required  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080088000Retired load instructions with L1 cache hits as data sources  Supports address when precise (Precise event)period=2000003,umask=0x1,event=0xb2Retired store instructions that miss the STLB  Supports address when precise (Precise event)period=50021,umask=0x10,event=0xd1offcore_response.demand_data_rd.l3_hit.spl_hitcmask=3,period=2000003,umask=0x1,event=0x9cperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFC408000period=100003,umask=0x10,event=0xb0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C400004offcore_response.demand_rfo.l3_miss.snoop_non_dramperiod=2000003,umask=0x20,event=0x54cmask=6,period=2000003,umask=0x6,event=0xa3period=2000003,umask=0x1,event=0xdCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1Counts resource-related stall cyclesperiod=2000003,umask=0x2,event=0xc2Counts when there is a transition from ring 1, 2 or 3 to ring 0Conditional branch instructions retired  Spec update: SKL091 (Precise event)64 * offcore_requests.all_requests / 1000000000 / duration_timeCounts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylakeperiod=2000003,umask=0x4,event=0x8Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request typeperiod=100007,umask=0x20,event=0xbdPage walk completed due to a demand data load to a 1G pagedtlb_load_misses.walk_activeThis event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)This event counts the number of store uops reissued from Rehabqumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000044offcore_response.pf_l2_data_rd.l2_miss.snoop_missumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000002Counts the number of JCC branch instructions retired (Precise event)This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this eventRetired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event)offcore_response.all_pf_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0122umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0004offcore_response.all_pf_rfo.llc_miss.dramoffcore_response.all_rfo.llc_miss.dramREQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIToffcore_response.pf_data_rd.llc_miss_local.dramThis event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel® 64 and IA-32 Architectures Optimization Reference ManualDirect and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event)sq_misc.lru_hintsREQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHEREQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAMREQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITMREQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAMREQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.pf_rfo.local_dram_and_remote_cache_hitREQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWDREQUEST = CORE_WB and RESPONSE = ANY_LLC_MISSumask=0x1,period=100000,event=0xb7,offcore_rsp=0xf850REQUEST = PF_DATA and RESPONSE = REMOTE_DRAMoffcore_response.pf_rfo.any_dram_and_remote_fwdumask=0x2,period=200000,event=0x3snoopq_requests_outstanding.invalidate_not_emptyCycles snoop invalidate requests queueditlb_misses.large_walk_completedumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2702period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0001offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_neededoffcore_response.pf_l2_rfo.l3_hit.hitm_other_coreNumber of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementoffcore_response.all_data_rd.l3_miss.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00491Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00400offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwdoffcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwdCore cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codesPipeline;PortsUtilMeasured Average Frequency for unhalted processors [GHz]Core Cross Snoops Issued; Multiple Core Requests. Unit: uncore_cha unc_cha_dir_lookup.snpunc_cha_imc_reads_count.normalumask=0x01,event=0x37Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busCounts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc1Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busfc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x84fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x84event=0x24event=0x25unc_m2m_direct2upi_takenunc_m2m_direct2upi_txn_overrideCounts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll)Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller)Cycles Intel UPI is in L1 power mode (shutdown). Unit: uncore_upi ll Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unitShows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting.offcore_response.all_pf_data_rd.l3_hit_e.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_reads.l3_hit_e.snoop_missoffcore_response.all_reads.l3_hit_f.no_snoop_neededoffcore_response.all_reads.l3_hit_m.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001007F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200122This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200001offcore_response.demand_data_rd.l3_hit_f.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.demand_data_rd.supplier_none.hit_other_core_fwdoffcore_response.demand_rfo.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.other.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200400offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200400offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_neededoffcore_response.pf_l1d_and_sw.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040010offcore_response.pf_l2_data_rd.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l2_rfo.l3_hit_f.snoop_noneoffcore_response.pf_l2_rfo.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwdNumber of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementocr.all_data_rd.l3_miss.any_snoopocr.all_data_rd.l3_miss.hit_other_core_no_fwdOCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITMOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01040007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x06040007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000122OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDEDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_missCounts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C008000ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_miss.snoop_missCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_noneoffcore_response.all_pf_data_rd.l3_miss.hitm_other_coreoffcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwdoffcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_neededoffcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwdoffcore_response.all_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITMoffcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdocr.all_data_rd.l3_hit_e.hit_other_core_fwdocr.all_data_rd.l3_hit_f.hit_other_core_no_fwdocr.all_data_rd.l3_hit_m.no_snoop_neededocr.all_data_rd.l3_hit_m.snoop_missOCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOPOCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwdocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwdocr.all_pf_data_rd.l3_hit_s.any_snoopocr.all_pf_data_rd.supplier_none.any_snoopocr.all_pf_rfo.l3_hit_e.snoop_missOCR.ALL_READS.L3_HIT_E.ANY_SNOOP  OCR.ALL_READS.L3_HIT_E.ANY_SNOOPOCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWDOCR.ALL_READS.L3_HIT_E.SNOOP_MISSocr.all_reads.pmm_hit_local_pmm.snoop_not_neededocr.all_rfo.l3_hit_e.snoop_missOCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_COREocr.all_rfo.l3_hit_s.snoop_noneocr.demand_code_rd.l3_hit_m.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORECounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_m.hit_other_core_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.demand_rfo.supplier_none.hitm_other_coreocr.other.l3_hit_e.hit_other_core_no_fwdocr.pf_l1d_and_sw.l3_hit_m.any_snoopocr.pf_l1d_and_sw.l3_hit_s.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORECounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_e.snoop_noneCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOPCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_COREocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_noneocr.pf_l3_data_rd.l3_hit_e.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit_m.snoop_missocr.pf_l3_data_rd.l3_hit_m.snoop_noneocr.pf_l3_data_rd.supplier_none.no_snoop_neededocr.pf_l3_data_rd.supplier_none.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONECounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDWrite requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_wpq_insertsIntel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all. Unit: uncore_imc Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory. Unit: uncore_imc Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores  Supports address when precise (Precise event)Number of L1D misses that are outstandingcmask=1,edge=1,period=100003,umask=0x30,event=0x79period=100003,umask=0x30,event=0x79Counts the number of times HLE commit succeededocr.hwpf_l2_rfo.l3_misscmask=6,period=1000003,umask=0x6,event=0xa3ocr.demand_code_rd.local_dramCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sentocr.hwpf_l2_data_rd.l3_hit.snoop_missCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.demand_code_rd.l3_hit.snoop_sentuops_dispatched.port_4_9Number of uops executed on port 5Counts far branch instructions retired (Precise event)Counts number of near branch instructions retired that were mispredicted and taken (Precise event)period=1000003,umask=0x80,event=0xa6Counts memory transactions sent to the uncoreCHA to iMC Full Line Writes Issued : Full Line Non-ISOCH. Unit: uncore_cha Lines Victimized : All Lines Victimized. Unit: uncore_cha umask=0xC001FD04,event=0x35unc_cha_tor_inserts.io_missunc_cha_tor_occupancy.iounc_cha_cms_clockticksumask=0xC80FFF01,event=0x35umask=0xC807FF01,event=0x36TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha umask=0xCD43FF04,event=0x35TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha Number Transactions requested by the CPU : Core reading from Card's MMIO space. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part5fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0x83unc_iio_data_req_of_cpu.mem_read.part7umask=0x0F,event=0x2umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010002period=200003,event=0xc5TOR Inserts; Code read from local IA that misses in the snoop filterTOR Inserts; Read for ownership from local IA that misses in the snoop filterTOR Inserts; RFO pref misses from local IA. Unit: uncore_cha TOR Inserts; Data read from local IA that misses in the snoop filterCounts the number of load uops retired that miss in the L2 cache  Supports address when precise (Precise event)Counts the total number of store uops retired  Supports address when precise (Precise event)Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event)edge=1,period=200003,event=0x63Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basisThis event is deprecatedCounts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event)Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cacheperiod=2000003,umask=0x20,event=0x85ic_fw32umask=0x00,event=0x90event=0xc6ex_ret_mmx_fp_instr.sse_instrfpu_pipe_assignment.dual3umask=0x10,event=0All Opsfp_ret_sse_avx_ops.allSingle precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSSingle-precision divide/square root FLOPSumask=0x10,event=0x45ls_pref_instr_disp.load_prefetch_wls_inef_sw_pref.data_pipe_sw_pf_dc_hitCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailableumask=0x02,event=0x85Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15Number of retired CLFLUSH instructionsls_rdtscls_pref_instr_disp.prefetchCore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2umask=0x3f,event=0x41ls_any_fills_from_sys.ext_cache_localumask=0x08,event=0xabCycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 availableL3 Cache Accesses. Unit: uncore_l3pmc l1_data_cache_fills_from_remote_nodemacro_ops_dispatchedDC_REFILL_FROM_SYSTEML1_ICACHE_REFILLCPU_CYCLESL2_CACHE_NEON_HITEVENT_10HEVENT_60HEVENT_6BHEVENT_76HEVENT_87HEVENT_95HEVENT_A1HEVENT_B6HEVENT_B9HEVENT_C0HEVENT_F0HL2D_CACHE_WB_CLEANUNALIGNED_ST_SPECPC_WRITE_SPECTAGCACHEMASTER_READ_RSPICACHE_HITEXCEPTIONSIFU_CYCLES_STALLEDSYSTEM_EVENT_2WBB_25_50_FULLSYNCVEC_LOAD_INSTR_COMPLETEDL2_STORE_HITSFPU_LONG_INSTR_COMPLETION_STALLCQ_REDIRECTSTAKEN_BRANCHES_FINISHEDBTB_HITS_PSEUDO_HITSCASTOUTS_RELEASEDtscprobe-hit-dirty-with-memory-cancelWRITEINTEL_PIVINTEL_IVYBRIDGE_XEONARMV7_CORTEX_A5STANDALONEmetric_name: %s
unrecognized kvpair: %s:%s
{"type": "procexec"%s, "pmcid": "0x%08x", "pid": "%d" "tid": "%d", "value": "0x%016jx"}
v15Unknown_BranchesAverage Frequency Utilization relative nominal frequencyAll L2 requestsThis event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFUThis is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)mem_load_uops_retired.l3_hitumask=0x8,period=100003,event=0xd2umask=0x5,period=100003,event=0xf2umask=0x2,period=2000003,event=0xc7umask=0x8,period=2000003,event=0xc7fp_assist.anyumask=0x24,cmask=4,period=2000003,event=0x79umask=0x24,cmask=1,period=2000003,event=0x79idq.ms_uopsCycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busymisalign_mem_ref.loadsNumber of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)umask=0x1,period=100003,event=0x7Cycles while L2 cache miss demand load is outstandingCycles at least 3 micro-op is executed from any thread on physical coreumask=0x40,period=100007,event=0xc4umask=0x3,event=0x35,filter_opc=0x18f,filter_nc=1llc_references.pcie_writewrite requests to remote home agent. Unit: uncore_ha Shared line response from remote cache. Unit: uncore_ha dtlb_load_misses.walk_completed_1gdtlb_load_misses.stlb_hit_4kdtlb_store_misses.walk_completed_2m_4mumask=0x10,period=100003,event=0x49This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend BoundThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPUAverage data fill bandwidth to the L2 cache [GB / sec]1000 * mem_load_uops_retired.l1_miss / inst_retired.anyRetired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)  Spec update: BDM100.  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020100offcore_response.pf_l3_code_rd.any_responseoffcore_response.other.supplier_none.snoop_hit_no_fwdoffcore_response.other.l3_hit.snoop_noneoffcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020120offcore_response.all_pf_rfo.l3_hit.snoop_hitmoffcore_response.all_pf_rfo.l3_hit.any_snoopoffcore_response.all_data_rd.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020091offcore_response.all_rfo.l3_hit.snoop_not_neededCounts randomly selected loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000020offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000080umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000100umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000028000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204008000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404008000offcore_response.all_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000091umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020122umask=0xc,period=2000003,cmask=12,event=0xa3Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCRetired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event)Counts all requests hit in the L3offcore_response.all_data_rd.llc_hit.hitm_other_coreumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC08FFFCounts all demand & prefetch data reads miss the L3 and the data is returned from remote dramevent=0x14unc_m_clockticksumask=0x50,period=200000,event=0x27l2_ifetch.self.i_stateL2 store requestsl2_reject_busq.self.any.m_stateumask=0x78,period=200000,event=0x30L1 Data reads and writesumask=0x8,period=200000,event=0x40l1d_cache.evictSIMD packed micro-ops retiredmisalign_mem_ref.bubbleprefetch.hw_prefetchumask=0x10,period=2000000,event=0x7umask=0x0,period=200000,event=0x62bus_trans_brd.all_agentsumask=0xe0,period=200000,event=0x6fumask=0x1,period=200000,event=0x77umask=0x2,period=200000,event=0x77umask=0x0,period=200000,event=0xc8cycles_div_busyumask=0x2,period=200000,event=0x89umask=0x10,period=2000000,event=0xc2umask=0x1,period=2000000,event=0xc4umask=0x1,period=2000000,event=0xe6Micro-op reissues on a store-load collision (At Retirement)data_tlb_misses.dtlb_miss_ldumask=0x1,period=2000000,event=0xcITLB misses (Must be precise)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cacheCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredoffcore_response.sw_prefetch.l2_miss.hitm_other_coreoffcore_response.sw_prefetch.l2_hitCounts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredhw_interrupts.maskedumask=0x8,period=200003,event=0x3Machine clears due to FP assistsumask=0xf7,period=200003,event=0xc4Retired mispredicted near return instructions (Precise event capable) (Must be precise)br_misp_retired.taken_jccCounts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returnsDuration of D-side page-walks in cyclesCounts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts all L2 code requestsDemand code read requests sent to uncoreThis event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)offcore_response.pf_l3_code_rd.l3_hit.any_responseoffcore_response.pf_l2_rfo.l3_hit.any_responseavx_insts.allCounts any FP_ASSIST umask was incrementing (Precise event)Randomly selected loads with latency value being above 64  Spec update: HSD76, HSD25, HSM26 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400122offcore_response.pf_l3_data_rd.l3_miss.any_responseloads blocked by overlapping with store buffer that cannot be forwardedNumber of SIMD move elimination candidate uops that were eliminatedCycles which a uop is dispatched on port 2 in this threadCycles with no micro-ops executed from any thread on physical core  Spec update: HSD30, HSM31L3 Lookup external snoop request that access cache and found line in I-stateCompleted page walks in any TLB of any page size due to demand load missesCompleted page walks due to store misses in one or more TLB levels of 4K page structureoffcore_response.demand_code_rd.llc_hit.hitm_other_coreNumber of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: HSD56, HSM57inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xeumask=0x3,period=200003,event=0x24umask=0x2,period=2000003,cmask=1,event=0x60Dirty L2 cache lines evicted by L2 prefetchumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10400Counts 256-bit packed double-precision floating-point instructionsuops_dispatched_port.port_0_coreuops_dispatched_port.port_1_coreuops_dispatched_port.port_3_coreumask=0x01,event=0x34Unit: uncore_cbox LLC lookup request that access cache and found line in E-stateunc_cbo_cache_lookup.sumask=0x01,cmask=10,event=0x80offcore_response.all_reads.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c03f7offcore_response.pf_llc_data_rd.llc_hit.hitm_other_coreCounts all data/code/rfo reads (demand & prefetch) that hit the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20001LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand. Unit: uncore_cbox umask=0x1,umask=0x3,event=0x1unc_p_freq_band3_cyclesfreq_band3_cycles %Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)l1d.allocated_in_mCycles when dispatched loads are cancelled due to L1D bank conflicts with other load portsSample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise)Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2Resource stalls due to memory buffers or Reservation Station (RS) being fully utilizedThis event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference ManualCounts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative pathCounts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800402000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080400offcore_response.uc_code_reads.l2_hit_near_tile_e_fCounts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateCounts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_rfo.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in E stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00040032f7umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000100Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.bus_locks.l2_hit_near_tileumask=0x1,period=100007,event=0xb7,offcore_rsp=0x18001832f7Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080803091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101008000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400200offcore_response.partial_writes.mcdram_faroffcore_response.pf_l2_code_rd.mcdram_nearCounts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit farCounts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181808000Fixed Counter: Counts the number of instructions retiredCounts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not readyumask=0xfd,period=200003,event=0xc5umask=0xbf,period=200003,event=0xc5umask=0x8,period=2000000,event=0x40l1d_cache_ld.s_stateAll L2 data requestsumask=0x20,period=200000,event=0xf0All L2 demand store RFOsumask=0x2,period=200000,event=0xcbSuper Queue lock splits across a cache lineoffcore_response.any_data.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x111umask=0x1,period=100000,event=0xb7,offcore_rsp=0x80FFoffcore_response.corewb.io_csr_mmioOffcore code or data read requests satisfied by the LLC and HIT in a sibling coreoffcore_response.data_in.any_cache_dramoffcore_response.data_in.llc_hit_other_core_hitoffcore_response.data_in.local_cacheoffcore_response.demand_data.io_csr_mmiooffcore_response.demand_ifetch.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4702Offcore other requests satisfied by the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3880offcore_response.other.remote_cache_hitmoffcore_response.pf_data.llc_hit_other_core_hitmumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4730umask=0x1,period=100000,event=0xb7,offcore_rsp=0x110offcore_response.pf_data_rd.remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1020umask=0x1,period=20000,event=0xf7X87 Floating point assists for invalid output value (Precise Event)fp_comp_ops_exe.sse_double_precisionfp_mmx_trans.to_fpoffcore_response.data_ifetch.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4077offcore_response.demand_data_rd.local_dramoffcore_response.pf_ifetch.local_drames_reg_renamesarith.mulTaken branches executedumask=0x1,period=20000,event=0x89SIMD Scalar-Double Uops retired (Precise Event)Stack pointer instructions decodeduops_decoded.esp_syncumask=0x10,any=1,period=2000000,event=0xb1DTLB miss page walksRetired loads that miss the DTLB (Precise Event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010004Retired load instructions missed L3 cache as data sources  Supports address when precise (Precise event)All retired store instructions  Supports address when precise (Precise event)offcore_response.demand_code_rd.l3_hit_e.any_snoopCounts the RFO (Read-for-Ownership) requests that hit L2 cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0028000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001C0001period=100007,umask=0x40,event=0xd1Retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event)period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100002offcore_response.demand_code_rd.l3_hit_s.snoop_hitmRetired load instructions with locked access  Supports address when precise (Precise event)Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementCounts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)period=100007,umask=0x1,event=0xc6,frontend=0x200206period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004008000offcore_response.other.l3_miss.any_snoopoffcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000001offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC4000002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x007C400001period=400009,umask=0x2,event=0xc5Cycles where the Store Buffer was full and no outstanding loadcmask=8,period=2000003,umask=0x8,event=0xa3cmask=4,period=2000003,umask=0x2,event=0xb1Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end1 - ( (idq_uops_not_delivered.core / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) + (( uops_issued.any - uops_retired.retire_slots + 4 * ( int_misc.recovery_cycles_any / 2 ) ) / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) + (uops_retired.retire_slots / (4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) )Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)idq.dsb_uops / (idq.dsb_uops + idq.mite_uops + idq.ms_uops)L3_Cache_Access_BWitlb_misses.walk_activeCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a storeperiod=100003,umask=0x20,event=0x49Page walk completed due to a demand data store to a 1G pageoffcore_response.pf_l2_code_rd.l2_miss.anyCounts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event)TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)RETURN counts the number of mispredicted near RET branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event countsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0244offcore_response.demand_code_rd.llc_hit.snoop_missoffcore_response.pf_llc_rfo.llc_hit.no_snoop_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch code reads that miss the LLC  and the data returned from dramoffcore_response.demand_rfo.llc_miss.dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400100offcore_requests_outstanding.any.readOutstanding offcore demand data readsSuper Queue LRU hints sent to LLCREQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_COREumask=0x1,period=100000,event=0xb7,offcore_rsp=0x150REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_RFO and RESPONSE = ANY_LOCATIONREQUEST = PF_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHEREQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3010umask=0x4,period=200000,event=0x8OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC00020offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063FC001001 / (inst_retired.any / cpu_clk_unhalted.thread)unc_iio_data_req_of_cpu.mem_read.part1unc_iio_data_req_of_cpu.mem_read.part2unc_iio_data_req_of_cpu.mem_read.part0 +unc_iio_data_req_of_cpu.mem_read.part1 +unc_iio_data_req_of_cpu.mem_read.part2 +unc_iio_data_req_of_cpu.mem_read.part3PCI Express bandwidth writing at IIO, part 2. Unit: uncore_iio unc_cha_rxc_inserts.irqRspCnflct* Snoop Responses Received. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data: Part 2fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc0Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_read.part3unc_iio_data_req_of_cpu.peer_write.part3Read request for up to a 64 byte transaction is made by the CPU to IIO Part2. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc1Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busPeer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit. Unit: uncore_iio Read request for up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cacheunc_i_transactions.wr_prefCycles when direct to Intel UPI was disabled. Unit: uncore_m2m umask=0x4,event=0x2dunc_upi_rxl_bypassed.slot2period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080491offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100491offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200490offcore_response.all_pf_data_rd.l3_hit_m.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_e.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08002007F7offcore_response.all_reads.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800207F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200122offcore_response.all_rfo.l3_hit_f.snoop_missoffcore_response.all_rfo.l3_hit_m.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100122This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONEoffcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwdoffcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwdoffcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C8000This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100010This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040020This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_data_rd.l3_miss.hitm_other_coreocr.all_data_rd.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000490period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000120OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISSperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000120ocr.all_pf_rfo.l3_miss_local_dram.snoop_missOCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C0007F7ocr.all_reads.l3_miss.snoop_noneocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwdocr.all_reads.l3_miss_remote_hop1_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00900007F7OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000001ocr.demand_data_rd.l3_miss.snoop_noneocr.other.l3_miss_local_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604008000Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDCounts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.other.l3_miss_remote_hop1_dram.snoop_noneocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000400ocr.pf_l2_data_rd.l3_miss.hitm_other_coreCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000010Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.all_reads.l3_miss.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.demand_rfo.l3_miss.hit_other_core_fwdoffcore_response.demand_rfo.l3_miss.hit_other_core_no_fwdoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.other.l3_miss_local_dram.hit_other_core_no_fwdoffcore_response.other.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdOCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_data_rd.pmm_hit_local_pmm.snoop_not_neededocr.all_data_rd.supplier_none.hit_other_core_no_fwdOCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_e.snoop_noneocr.all_pf_data_rd.l3_hit_f.no_snoop_neededocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwdocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoopOCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_neededocr.all_pf_rfo.any_responseOCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDEDOCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_reads.l3_hit_e.snoop_missocr.all_reads.l3_hit_s.snoop_noneOCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_rfo.supplier_none.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORECounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.supplier_none.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.other.l3_hit.any_snoopCounts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWDCounts any other requests  OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDEDCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISSocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwdocr.pf_l1d_and_sw.l3_hit_e.no_snoop_neededocr.pf_l1d_and_sw.l3_hit_s.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l2_data_rd.l3_hit.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_s.snoop_missCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOPIntel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc umask=0x1,event=0xe0unc_m_pmm_read_latencyunc_m_pmm_cmd1.rdumask=0x1,event=0xe4All dirty line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc unc_iio_data_req_of_cpu.mem_write.part0 + unc_iio_data_req_of_cpu.mem_write.part1 + unc_iio_data_req_of_cpu.mem_write.part2 + unc_iio_data_req_of_cpu.mem_write.part3unc_iio_data_req_of_cpu.mem_read.part0 + unc_iio_data_req_of_cpu.mem_read.part1 + unc_iio_data_req_of_cpu.mem_read.part2 + unc_iio_data_req_of_cpu.mem_read.part3Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3l2_rqsts.swpf_missCounts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITESpeculatively counts the number of TSX aborts due to a data capacity limitation for transactional readsperiod=100003,umask=0x1,event=0x32Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1E003C0020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1E003C0010Number of occurrences where a microcode assist is invoked by hardwareCounts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event)Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in usecpu_clk_unhalted.ref_distributedCore crystal clock cycles. Cycle counts are evenly distributed between active threads in the CoreCounts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB)Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle1 / ipc1000000000 * ( unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_inserts.ia_miss_drd ) / ( cha_0@event\=0x0@ / duration_time )TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC. Unit: uncore_cha umask=0xC807FD01,event=0x35unc_cha_tor_inserts.ia_miss_llcprefrfoumask=0xCD43FE04,event=0x35umask=0xC8170A01,event=0x35unc_cha_tor_inserts.ia_miss_llcprefdataTOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC. Unit: uncore_cha unc_iio_data_req_of_cpu.cmpd.part3unc_iio_txn_req_of_cpu.cmpd.part1fc_mask=0x07,ch_mask=0x20,umask=0x80,event=0x83unc_iio_txn_req_by_cpu.mem_write.part5unc_iio_comp_buf_occupancy.cmpd.part4PCIe Completion Buffer Occupancy of completions with data : Part 0-7. Unit: uncore_iio umask=0x10,event=0x1fumask=0x40,event=0x10umask=0x04,event=0x2dumask=0x4,period=200003,event=0xd1Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new lineData requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1Counts the number of times there was an ITLB miss and a new translation was filled into the ITLBperiod=200003,umask=0x4,event=0xe6period=200003,event=0xe8Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branchCounts the number of core cycles during which interrupts are masked (disabled)Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of responsetopdown_bad_speculation.fastnukeperiod=1000003,umask=0x8,event=0x74period=200003,umask=0x20,event=0x8period=200003,umask=0x4,event=0x8period=2000003,umask=0x4,event=0x85Counts the number of load ops retired that miss in the second Level TLB  Supports address when precise (Precise event)l2_request_g1.all_no_prefetchumask=0x02,event=0x64umask=0x80,event=0x1xi_ccx_sdp_req1.all_l3_miss_req_typsex_ret_brn_resyncRetired Indirect Branch Instructions Mispredictedumask=0x04,event=0x1cfRemote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3dram_channel_data_controller_3This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPSSingle-precision add/subtract FLOPSL1 DTLB Miss of a page of 32K sizeThe number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request bufferde_dis_dispatch_token_stalls0.retire_token_stallde_dis_dispatch_token_stalls0.agsq_token_stallumask=0x07,event=0x29L2 Cache Misses from L2 HWPFumask=0xf0,event=0x45Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPSls_bad_status2.stli_otherde_dis_uop_queue_empty_di0event=0xa9de_dis_uops_from_decoderde_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stallCore to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses insteadex_ret_opsAdd/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventCounts the number of interrupts takenumask=0x10,event=0x44Count of Allocated MabsAll TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed insteadCycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 availablebp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_missFR_DISPATCH_STALLSFR_DISPATCH_STALL_WHEN_LS_IS_FULLNB_MEMORY_CONTROLLER_BYPASS_SATURATIONEXC_TAKENEVENT_43HEVENT_52HEVENT_71HEVENT_94HEVENT_A6HDATA_CACHE_DEPENDENT_STALLL1D_TLBITLB_WALKL1D_TLB_RDL2D_TLB_REFILL_WRDCACHE_SET_TAG_READDC_LOADSTOREITLB_ACCESSESDDQ0_FULL_DR_STALLSLOAD_STORE_BLOCKED_CYCLESCP1_BRANCH_MISPREDICTIONSONE_INSN_CYCLESSYSTEM_EVENT_4LDSSPEC_BUFFER_CYCLESITLB_HW_TABLE_SEARCH_CYCLESBRANCH_LINK_STACK_CORRECTLY_RESOLVEDITLB_HW_SEARCH_CYCLES_OVER_THRESHOLDL2_DATA_CACHE_MISSESSNOOP_MODIFIEDBORDQ_FULLBUS_TAS_FOR_WRITESBUS_READS_WRITES_NOT_RETRIEDPREFETCH_ENGINE_REQUESTFPU_MARKED_INSTR_COMPLETEDCYCLES_WITH_ANY_THREAD_RUNNINGBRANCHES_FINISHEDLOAD_GUARDED_MISS_CYCLESBIU_MASTER_DATA_SIDE_CASTOUT_REQUESTSEXT_INPU_INTR_LATENCY_CYCLESmask=TSCARMV8MIPS74KINTEL_WESTMERE_EXMIPS_24KARMV7_CORTEX_A9%s:
%s
frontend"0x%016jx"]}
GenuineIntel-6-1FGenuineIntel-6-8[CD]UPIidq.dsb_uops / ( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops )C6 residency percent per packageC7_Pkg_ResidencyCycles with L1D load Misses outstandingl1d.replacementumask=0x1,period=2000003,event=0x51Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)  Supports address when precise (Precise event)Number of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: BDM30umask=0x4,cmask=1,period=2000003,event=0x79This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQtx_mem.abort_hle_elision_buffer_not_emptyumask=0x1,period=2000003,event=0x5dNumber of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details)This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. 
Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. 
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructionsumask=0x1,period=100003,event=0x4cThis event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructionsumask=0x2,period=1000003,event=0x58Stalls caused by changing prefix length of the instructionThis event counts taken speculative and retired macro-conditional branch instructionsbr_inst_exec.taken_direct_near_callumask=0xc8,period=200003,event=0x88Cycles per thread when uops are executed in port 3umask=0x1,cmask=4,period=2000003,event=0xa8Cycles Uops delivered by the LSD, but didn't come from the decoderCycles with less than 10 actually retired uopsThis event counts not taken branch instructions retiredbr_misp_retired.retwrite requests to home agent. Unit: uncore_ha M line forwarded from remote cache with no writeback to memory. Unit: uncore_ha (unc_p_power_state_occupancy.cores_c0 / unc_p_clockticks) * 100.virtual memoryStore miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69umask=0x4,period=100003,event=0x49itlb_misses.miss_causes_a_walkThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the BackendBackend_Bound_SMTPGO;IcMissCycles Per Instruction (per Logical Processor)L3MPKIumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0001offcore_response.corewb.supplier_none.snoop_not_neededoffcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0120offcore_response.all_pf_code_rd.any_responseoffcore_response.all_pf_code_rd.supplier_none.snoop_hitmoffcore_response.all_rfo.l3_hit.snoop_hit_no_fwdThis is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalidCounts randomly selected loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000001offcore_response.demand_code_rd.l3_miss.snoop_missoffcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dramoffcore_response.pf_l2_code_rd.supplier_none.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020040offcore_response.pf_l3_data_rd.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000200offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_missoffcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000122umask=0x2,period=2000003,cmask=2,event=0xb1umask=0x2f,event=0x34Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficoffcore_response.demand_rfo.llc_hit.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x06040007F7umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000244This event counts conditional branch instructions retired (Precise event)This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event)l2_ld.self.any.m_stateumask=0x42,period=200000,event=0x29umask=0x44,period=200000,event=0x2cl2_data_rqsts.self.s_stateumask=0x51,period=200000,event=0x2eumask=0x41,period=200000,event=0x2el2_reject_busq.self.any.mesiumask=0x48,period=200000,event=0x30umask=0xa3,period=2000000,event=0x40L1 Data line replacementsumask=0x2,period=10000,event=0xcbumask=0x80,period=2000000,event=0xb0umask=0x81,period=2000000,event=0xb3SIMD packed arithmetic micro-ops executedRetired Streaming SIMD Extensions (SSE) packed-single instructionsumask=0x0,period=100000,event=0xcdNon-CISC nacro instructions decodedAll Instructions decodedumask=0xf,period=200000,event=0x5umask=0x94,period=200000,event=0x5umask=0x82,period=200000,event=0x7bus_request_outstanding.selfbus_hitm_drv.this_agentumask=0x0,period=200000,event=0x7bbusq_empty.selfumask=0x1,period=200000,event=0x3cbr_inst_type_retired.condBranch instructions decodedL0 DTLB misses due to load operationspage_walks.walksCounts data reads (demand & prefetch) that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008000offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400001000offcore_response.partial_reads.l2_miss.anyoffcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwdCounts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=200003,event=0x80Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translationumask=0x1,period=200003,event=0x3Loads blocked due to store data not ready (Precise event capable) (Must be precise)br_inst_retired.all_taken_branchesCounts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise)cycles_div_busy.fpdivCycles the FP divide unit is busyCounts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystemCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004800Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.any_responseCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Machines clear due to a page faultumask=0x8,period=200003,event=0x8Demand requests that miss L2 cache  Spec update: HSD78Counts all L2 HW prefetcher requestsThis event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performanceThis event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis  Spec update: HSD135Randomly selected loads with latency value being above 128  Spec update: HSD76, HSD25, HSM26 (Must be precise)Number of flags-merge uops allocated. Such uops add delayUnit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor coreL3 Lookup external snoop request that access cache and found line in M-stateUnit: uncore_arb Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)Store misses in all DTLB levels that cause completed page walks (2M/4M)page_walker_loads.ept_dtlb_l1Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Offcore outstanding Demand Data Read transactions in uncore queueCycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncoremem_load_uops_llc_hit_retired.xsnp_hitmDirty L2 cache lines filling the L2Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0001fp_comp_ops_exe.sse_scalar_singleumask=0x1,period=2000003,event=0x11number of GSSE-256 Computational FP single precision uops issued this cycleumask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400004Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)Cycles per core when uops are dispatched to port 4Cycles Allocation is stalled due to Resource Related reasonumask=0x01,event=0x22Filter on cross-core snoops initiated by this Cbox due to processor core memory requestLLC lookup request that access cache and found line in M-statedtlb_load_misses.large_page_walk_completedMiss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)offcore_response.all_pf_data_rd.llc_hit.any_responseCounts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c03f7offcore_response.all_reads.llc_hit.snoop_missCounts demand data reads that miss the LLC  and the data returned from remote & local dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400010umask=0x1,event=0x35,filter_opc=0x195event=0xe,edge=1Counts the number of cycles that the uncore was running at a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu Allocated L1D data cache lines in M stateSpeculative and retired mispredicted direct near callsbr_misp_retired.takenumask=0x2,period=100003,event=0xc1This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this typeoffcore_response.any_pf_l2.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080070Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts Demand code reads and prefetch code read requests  that accounts for any responseCounts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800403091umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080200Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_code_rd.l2_hit_far_tile_mCounts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000070umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000001umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000400offcore_response.any_data_rd.l2_hit_this_tile_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180400umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800182000Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeCounts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800402000umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200044Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800080umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200004umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800002Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP (Precise event)no_alloc_cycles.not_deliveredumask=0x1f,period=200003,event=0xcb6.4e-05MiBCounts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be includedL1 data cache stores in E statel2_data_rqsts.demand.i_statel2_data_rqsts.prefetch.m_statel2_lines_in.e_stateL2 lines allocated in the E stateumask=0x4,period=200000,event=0x6Memory instructions retired above 16384 clocks (Precise Event)mem_inst_retired.latency_above_threshold_2048mem_inst_retired.latency_above_threshold_4umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F11Offcore data reads that HIT in a remote cacheAll offcore code readsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x10FFoffcore_response.any_request.remote_cache_hitmOffcore RFO requests that HITM in a remote cacheoffcore_response.demand_data.any_cache_dramoffcore_response.demand_data.llc_hit_other_core_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x201offcore_response.demand_data_rd.remote_cacheoffcore_response.demand_ifetch.any_cache_dramoffcore_response.demand_rfo.io_csr_mmiooffcore_response.demand_rfo.local_cache_dramOffcore prefetch data requests that HITM in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x140All offcore prefetch RFO requestsumask=0x1,period=100000,event=0xb7,offcore_rsp=0x820offcore_response.prefetch.local_cache_dramOffcore requests that missed the LLCOffcore RFO requests satisfied by a remote DRAMOffcore demand data reads that missed the LLCoffcore_response.demand_rfo.any_dramOffcore prefetch data reads satisfied by any DRAMoffcore_response.pf_data_rd.local_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x6020load_dispatch.anyload_dispatch.mobumask=0x1,period=100000,event=0xb8umask=0x2,period=20000,event=0x89ROB full stall cyclesumask=0x8,period=200000,event=0xc7uops_executed.core_stall_countperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040400004cmask=1,period=2000003,umask=0x8,event=0x60period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001C0001Counts the total number of requests from the L2 hardware prefetchersperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000400002offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC01C0001offcore_response.other.l3_hit_s.snoop_missoffcore_response.demand_rfo.supplier_none.snoop_hitmoffcore_response.demand_rfo.supplier_none.snoop_noneperiod=200003,umask=0xc1,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040001Counts retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event)period=2000003,umask=0x2,event=0xc7cmask=1,edge=1,period=2000003,umask=0x30,event=0x79period=100007,umask=0x1,event=0xc6,frontend=0x404006period=2000003,umask=0x30,event=0x79period=2000003,umask=0x8,event=0xc9period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000408000period=503,umask=0x1,event=0xcd,ldlat=0x100period=2000003,umask=0x1,event=0xc9period=2000003,umask=0x20,event=0xecmask=1,period=2000003,umask=0x1,event=0xa8cmask=3,period=2000003,umask=0x2,event=0xb1Core crystal clock cycles when this thread is unhalted and the other thread is haltedNumber of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)  Spec update: SKL091, SKL044 (Must be precise)period=2000003,umask=0x20,event=0xccexe_activity.1_ports_util4 * ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )l1d_pend_miss.pending / ( mem_load_retired.l1_miss + mem_load_retired.fb_hit )Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitectureCycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in SkylakeCode miss in all TLB levels causes a page walk that completes. (All page sizes)period=2000003,umask=0x2,event=0x8Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.)rehabq.ld_block_st_forwardCounts the number of mispredicted taken JCC branch instructions retired (Precise event)IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-opsStalls due to FP assistsCounts the number of JCC baclearsLoads missed DTLB (Precise event)offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwdoffcore_response.all_pf_code_rd.llc_hit.hitm_other_coreCounts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.data_in.any_responseREQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1ffREQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAMoffcore_response.pf_data.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f50umask=0x2,period=200000,event=0x5REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDoffcore_response.other.any_dram_and_remote_fwdumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4080Outstanding snoop data requestsumask=0x1,period=2000000,cmask=1,event=0xb3umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5844umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5804period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0010offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0100offcore_response.all_data_rd.l3_miss.remote_hitmoffcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800490Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_rfo.l3_miss.remote_hitmoffcore_response.demand_rfo.l3_miss.remote_hit_forwardCounts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dramCounts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dramCore cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo scheduleFlopsuops_executed.thread / (( uops_executed.core_cycles_ge_1 / 2 ) if #smt_on else uops_executed.core_cycles_ge_1)DRAM Page Activate commands sent due to a write request. Unit: uncore_imc unc_cha_clockticksumask=0x04,event=0x50fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x83fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x83umask=0x08,event=0x37PCIe Completion Buffer occupancy of completions with data: Part 1. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part2unc_iio_data_req_by_cpu.peer_write.part3unc_iio_data_req_of_cpu.peer_write.part1Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory. Unit: uncore_iio fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x84Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busevent=0x18unc_m2m_bypass_m2m_egress.not_takenMulti-socket cacheline Directory lookup (cacheline found in I state). Unit: uncore_m2m unc_m2m_directory_update.s2iunc_m2m_rxc_ad_occupancyBL Egress (to CMS) Allocations; Allunc_m3upi_upi_prefetch_spawnCounts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save powerCounts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save powerThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020490This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_f.snoop_noneoffcore_response.all_pf_rfo.l3_hit_m.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400120This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0122offcore_response.all_rfo.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200122offcore_response.all_rfo.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0001offcore_response.demand_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_e.hitm_other_coreoffcore_response.other.l3_hit_m.hitm_other_coreoffcore_response.other.l3_hit_m.hit_other_core_fwdoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_neededoffcore_response.pf_l1d_and_sw.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020010offcore_response.pf_l2_rfo.l3_hit_f.any_snoopoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200100This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000491OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOPocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000490ocr.all_rfo.l3_miss.no_snoop_neededOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.demand_code_rd.l3_miss_local_dram.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_neededCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOPocr.other.l3_miss_remote_hop1_dram.hitm_other_coreocr.pf_l1d_and_sw.l3_miss.snoop_noneocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_missocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwdocr.pf_l2_data_rd.l3_miss.snoop_noneCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITMCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss_local_dram.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000100offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss.hitm_other_coreoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoopOCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDOCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.all_data_rd.l3_hit_e.snoop_missOCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOPOCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOPocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwdOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREOCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOPOCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISSocr.all_reads.supplier_none.hit_other_core_no_fwdocr.all_rfo.l3_hit.any_snoopOCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWDOCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDEDCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOPocr.demand_code_rd.l3_hit_f.snoop_missocr.demand_code_rd.l3_hit_s.snoop_missCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOPCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONECounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_f.any_snoopocr.demand_data_rd.l3_hit_s.hit_other_core_fwdCounts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.other.any_responseCounts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwdocr.pf_l2_data_rd.l3_hit_m.hitm_other_coreocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwdocr.pf_l2_data_rd.l3_hit_s.no_snoop_neededocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISSocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwdocr.pf_l2_rfo.l3_hit_f.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l3_data_rd.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDunc_m_pmm_cmd1.ufill_rdTOR Inserts : DRds issued by iA Cores that Missed the LLC. Unit: uncore_cha Write requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)Counts retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event)Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitionsNumber of switches from DSB or MITE to the MSCounts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accessesperiod=100003,umask=0x80,event=0x54Counts the number of times an RTM execution aborted due to HLE-unfriendly instructionsocr.hwpf_l2_data_rd.l3_hit.anyperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000004period=10000003,umask=0x4,event=0period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC03C0002This event counts cycles without actually retired instructionsCounts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this casecmask=1,period=2000003,umask=0x3,event=0xdCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand loadCounts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycleunc_m_dram_refresh.panicRemote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent. Unit: uncore_cha Local write requests that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_inserts.io_hitumask=0xC001FE04,event=0x35umask=0xC001FE04,event=0x36TOR Inserts : ItoMs issued by IO Devices. Unit: uncore_cha umask=0xC8177E01,event=0x35TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices. Unit: uncore_cha unc_iio_data_req_of_cpu.cmpd.part0unc_iio_txn_req_by_cpu.mem_write.part6fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0xc1umask=0x04,event=0xfunc_i_snoop_resp.all_hit_mumask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010001Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event)umask=0xC86FFE01,event=0x35Clockticks of the IO coherency tracker (IRP)Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/MCounts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/Mperiod=20003,umask=0x2,event=0xc3ocr.demand_data_and_l1pf_rd.l3_missocr.demand_rfo.l3_miss_localCounts the number of issue slots every cycle that were not consumed by the backend due to branch mispredictsCounts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branchperiod=1000003,event=0xc2period=200003,umask=0xf9,event=0xc4period=2000003,umask=0x2,event=0x85ic_cache_fill_l2All L2 Cache Requests (Breakdown 1 - Common). Data cache shared readsumask=0x04,event=0x60umask=0x08,event=0x61Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2umask=0xff,event=0x4event=0xd4ex_tagged_ibs_ops.ibs_tagged_opsTotal number of fp uOps on pipe 3The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1fp_num_mov_elim_scal_op.opt_potentialumask=0x01,event=0x5event=0x47Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailableMicro-ops DispatchedRetired Conditional Branch Instructions MispredictedTotal number uOps assigned to pipe 1Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesumask=0x02,event=0xeumask=0x08,event=0x25umask=0x04,event=0x25Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedls_smi_rxA non-cacheable store and the non-cacheable commit buffer is fullumask=0x10,event=0x43L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLBumask=0x01,event=0x5als_tlb_flushevent=0x1c7Retired Mispredicted Branch Instructions due to Direction MismatchDivide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventSoftware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Nodels_sw_pf_dc_fills.int_cacheCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semanticsDC_MICROARCHITECTURAL_EARLY_CANCELWRITE_BUF_FULLEVENT_0FHEVENT_3EHEVENT_4BHEVENT_4FHEVENT_86HEVENT_93HEVENT_C5HNEON_INSTRS_RENAMEDL1I_CACHE_REFILLBR_INDIRECT_SPECBR_RETURN_RETIREDDP_SPECBR_MIS_PRED_RETIREDL2D_TLBL3_CACHE_RDUNREPRESENTABLE_CAPSL2CACHE_WRITE_MISSL2CACHE_SET_TAG_READL2CACHEMASTER_WRITE_RSPTAGCACHEMASTER_WRITE_REQCACHE_STALL_CYCLESWBB_GT_HALFREDIRECT_STALLSCOND_BRANCH_INSNSGFIFO_BLOCKED_CYCLESCP1_CP2_STORE_INSNSIFIBRMISLSU_ALIAS_VS_CSQL1_DATA_CYCLES_USEDFPR_ISSUE_STALLEDTAKEN_BRANCHES_PROCESSEDBRANCH_FLUSHESFPU_COMPLETION_STALLCACHE_LOAD_MISSLOADS_TRANSLATED_ALLOCATED_TO_DLFBSTORES_COMPLETED_ALLOCATED_TO_DLFBSTORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLESL2_CACHE_DATA_DIRTY_HITSpacked-sse-sse2commandINTEL_PIIIINTEL_ATOM_SILVERMONTARMV8_CORTEX_A76RUNNINGbad magicLLC_REFERENCEex_ret_instrcmaskconfig1GenuineIntel-6-47GenuineIntel-6-2FGenuineIntel-6-7EFraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)2* ( rs_events.empty_cycles - icache.ifdata_stall  - ( 14 * itlb_misses.stlb_hit + cpu@itlb_misses.walk_duration\,cmask\=1@ + 7* itlb_misses.walk_completed ) ) / rs_events.empty_endLoad_Miss_Real_LatencyFLOPS;Summaryumask=0x21,period=200003,event=0x24umask=0xf8,period=200003,event=0x24l2_rqsts.referencesThis event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoMumask=0x11,period=100003,event=0xd0umask=0x4,period=200003,event=0xf0fp_arith_inst_retired.scalar_doubleumask=0x3,period=2000003,event=0xc7mem_trans_retired.load_latency_gt_4umask=0x1,period=50021,event=0xcd,ldlat=0x8mem_trans_retired.load_latency_gt_256mem_trans_retired.load_latency_gt_512umask=0x1,period=2000003,event=0x5cThis event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such accessumask=0x0,period=2000003,event=0x3cThis is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhzbr_inst_exec.all_indirect_near_returnSpeculative and retired direct near callsbr_misp_exec.taken_indirect_jump_non_call_retTaken speculative and retired mispredicted indirect branches excluding calls and returnsuops_dispatched_port.port_3umask=0x40,any=1,period=2000003,event=0xa1umask=0x10,period=2000003,event=0xa2FP operations  retired. X87 FP operations that have no exceptions:Self-modifying code (SMC) detectedAll (macro) branch instructions retired. (Precise Event - PEBS)  Spec update: BDW98 (Must be precise)uncore cacheumask=0x1,event=0x35,filter_opc=0x1c8,filter_tid=0x3eOccupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rspsprochot_external_cycles %unc_p_freq_max_os_cyclesumask=0x40,period=2000003,event=0x8Code miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPUbr_inst_retired.all_branches / br_inst_retired.near_takeninst_retired.any / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))Actual Average Latency for L1 data-cache miss demand loads (in core cycles)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Spec update: BDM100.  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0002umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0002offcore_response.corewb.supplier_none.snoop_noneoffcore_response.corewb.l3_hit.snoop_not_neededoffcore_response.pf_l3_data_rd.l3_hit.snoop_not_neededCounts all prefetch (that bring data to LLC only) RFOsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0100offcore_response.pf_l3_code_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0090Counts prefetch RFOsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020120offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwdoffcore_response.all_pf_code_rd.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020122umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020122This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist interventionumask=0x24,period=2000003,cmask=1,event=0x79offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_neededoffcore_response.corewb.l3_miss_local_dram.snoop_noneoffcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000200offcore_response.other.l3_miss.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000090offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_neededoffcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000120offcore_response.all_pf_code_rd.l3_miss.snoop_not_neededumask=0x4,period=2000003,cmask=4,event=0xa3unc_cbo_cache_lookup.read_mUnit: uncore_cbox L3 Lookup read request that access cache and found line in M-stateunc_cbo_cache_lookup.any_munc_arb_trk_occupancy.allRetired store uops that split across a cacheline boundary  Supports address when precise (Precise event)Counts all demand & prefetch code reads miss in the L3Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00122Counts all demand data writes (RFOs) miss in the L3Mispredicted conditional branch instructions retired (Precise event)umask=0x40,period=200000,event=0x22umask=0x40,period=200000,event=0x24L2 cache line modificationsumask=0x7f,period=200000,event=0x29l2_ld.self.demand.s_statel2_st.self.e_statel2_reject_busq.self.demand.mesisimd_uops_exec.sumask=0x2,period=2000000,event=0xb3umask=0x2,period=2000000,event=0xc7macro_insts.non_cisc_decodedld-op-st splitsprefetch.prefetcht1umask=0x88,period=200000,event=0x7L1 hardware prefetch requestbus_bnr_drv.all_agentsumask=0xe0,period=200000,event=0x6bBus stalled for snoopsumask=0x2,period=2000000,event=0xc6br_inst_type_retired.retumask=0x10,period=2000000,event=0x88umask=0x8,period=200000,event=0x89Mispredicted and taken cond branch instructions retiredRetired branch instructions that were predicted not-takenpage_walks.cyclesitlb.flushcore_reject_l2q.allCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040022offcore_response.any_pf_data_rd.l2_hitoffcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_neededCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000002Unfilled issue slots per cycleumask=0x8,period=200003,event=0xc3umask=0x80,period=200003,event=0xc4Counts near return branch instructions retired (Must be precise)BACLEARs asserted for any branch typeoffcore_response.pf_l2_data_rd.outstandingCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystemCounts data cache lines requests by software prefetch instructions hit the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004800Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x10,period=200003,event=0x4fDemand RFO read requests sent to uncore, including regular RFOs, locks, ItoMAll retired load uops. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor coreThis event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walksNumber of DTLB page walker hits in the L3 + XSNP  Spec update: HSD25Number of near branch instructions retired that were taken but mispredicted (Precise event)Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event)Counts all demand & prefetch prefetch RFOsfp_comp_ops_exe.sse_packed_singlenumber of AVX-256 Computational FP double precision uops issued this cycleNumber of assists associated with 256-bit AVX store operationsNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesLoads with latency value being above 256 (Must be precise)umask=0x2,period=2000003,event=0xcdLLC lookup request that access cache and found line in S-stateunc_cbo_cache_lookup.any_request_filterumask=0x84,period=2000003,event=0x8Cycle PMH is busy with a walk due to demand loadsCounts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x23ffc08000Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dramCounts all demand code reads that miss the LLC  and the data returned from remote dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20200umask=0x3,event=0x35,filter_opc=0x1e4unc_p_freq_max_current_cycles(unc_p_freq_max_current_cycles / unc_p_clockticks) * 100.Counts the number of cycles that the uncore was running at a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu All retired store uops (Precise event)l1d.all_m_replacementMultiply packed/scalar single precision uops allocatedresource_stalls2.bob_fullDirect and indirect mispredicted near call instructions retired (Precise event)l2_requests_reject.allumask=0x10,period=200003,event=0x4umask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032f7Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800088000offcore_response.pf_l1_data_rd.l2_hit_near_tile_mCounts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.bus_locks.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000200offcore_response.partial_writes.any_responseumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400040umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000080offcore_response.uc_code_reads.l2_hit_this_tile_eCounts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in E stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000020Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_read.l2_hit_this_tile_fCounts the number of times the MSROM starts a flow of uopsoffcore_response.any_rfo.ddr_nearCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Faroffcore_response.partial_reads.ddr_nearoffcore_response.demand_code_rd.mcdram_faroffcore_response.demand_data_rd.mcdram_farumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180603091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far)umask=0x20,period=200003,event=0xc2br_misp_retired.far_branchl1d_cache_lock.hitL2 RFO missesl2_transactions.wbmem_uncore_retired.remote_dramumask=0x10,period=2000000,event=0xb,ldlat=0x0umask=0x1,period=100000,event=0xb7,offcore_rsp=0x411offcore_response.any_data.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x444offcore_response.any_ifetch.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x18FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F22offcore_response.any_rfo.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x8033Offcore request = all data, response = remote cacheoffcore_response.demand_data.remote_cache_hitmOffcore demand data reads satisfied by the LLC  and HITM in a sibling coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4701umask=0x1,period=100000,event=0xb7,offcore_rsp=0x404umask=0x1,period=100000,event=0xb7,offcore_rsp=0x704Offcore prefetch data requests satisfied by the IO, CSR, MMIO unitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F40umask=0x20,period=2000000,event=0x10umask=0x4,period=200000,event=0xfdOffcore data reads that missed the LLCumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4044offcore_response.corewb.remote_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x4001umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2080umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6040io_transactionssnoop_response.hitmInstruction queue forced BACLEARInstructions written to instruction queueumask=0x1,period=200000,event=0x4cresource_stalls.otherumask=0x1,period=2000000,event=0xb1uops_executed.port1umask=0x1,period=2000000,event=0xedtlb_misses.anymem_store_retired.dtlb_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020002mem_load_retired.l3_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010002period=100003,umask=0x4f,event=0x2eperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0020002period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC0088000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801C0001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400400001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080408000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080002offcore_response.demand_rfo.l3_hit_e.any_snoopCounts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1period=100007,umask=0x1,event=0xc6,frontend=0x11cmask=1,period=2000003,umask=0x18,event=0x79Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event)Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MSCycles while L3 cache miss demand load is outstandingperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2004000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C400001offcore_response.demand_data_rd.l3_miss.spl_hitNumber of hardware interrupts received by the processorperiod=2000003,umask=0x1,event=0xa1Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7cmask=20,period=2000003,umask=0x14,event=0xa3uops_executed.thread / ( uops_executed.core_cycles_ge_1 / 2 )Fraction of cycles spent in the Operating System (OS) Kernel modeperiod=100003,umask=0xe,event=0x8Loads blocked due to store data not readyUops with lock semanticsoffcore_response.any_data_rd.l2_miss.snoop_missCounts streaming store that miss L2Counts DCU hardware prefetcher data read that miss L2Counts demand and DCU prefetch instruction cacheline that miss L2Counts demand and DCU prefetch data read that have any response typeThis event counts the number of times that pipeline was cleared due to memory ordering issuesCounts the number of branch instructions retired.. (Precise event)Counts all machine clearsCycles the divider is busy.  Does not imply a stall waiting for the dividerCounts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REFCounts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0120Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0122Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_requests.demand.read_dataoffcore_requests_outstanding.demand.read_codeREQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIOumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f22umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f08REQUEST = CORE_WB and RESPONSE = LOCAL_CACHEREQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIToffcore_response.demand_ifetch.local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0x5002REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAMREQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISSoffcore_response.any_rfo.any_dram_and_remote_fwdREQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAMREQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwdoffcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwdoffcore_response.all_pf_rfo.l3_hit.hitm_other_coreCounts demand data reads that hit in the L3offcore_response.pf_l1d_and_sw.any_responseOFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWDCounts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0080offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructionsperiod=100003,umask=0x4,event=0xfeFlops;FpArith;InsTypeMemoryTLBL2_Evictions_Silent_PKIDRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode. Unit: uncore_imc unc_cha_requests.writesPCI Express bandwidth writing at IIO, part 1. Unit: uncore_iio unc_cha_dir_update.haCounts number of allocations per cycle into the specified Ingress queueunc_cha_sf_eviction.s_stateunc_cha_snoop_resp.rspcnflctsPCIe Completion Buffer occupancy of completions with data: Part 2unc_iio_data_req_by_cpu.mem_write.part0Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part2fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x83fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x83fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc1fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc1Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busWrite request of up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x84unc_iio_txn_req_of_cpu.peer_write.part3unc_m2m_imc_reads.normalThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0490offcore_response.all_pf_data_rd.l3_hit_m.snoop_missoffcore_response.all_pf_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_pf_data_rd.supplier_none.hitm_other_coreoffcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwdoffcore_response.all_pf_rfo.l3_hit_s.snoop_noneoffcore_response.all_reads.l3_hit.snoop_hit_with_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISSoffcore_response.all_reads.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0004offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080001offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200001offcore_response.demand_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020400This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwdoffcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwdoffcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_neededoffcore_response.pf_l2_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_s.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040080period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100080offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_neededclx metricsMemoryLat;SoC;Serverocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C0007F7ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_neededocr.all_rfo.l3_miss.hitm_other_coreocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000122period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000004ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORECounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdocr.other.l3_miss.hitm_other_coreocr.other.l3_miss.no_snoop_neededCounts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000010Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000020ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000100offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_remote_hop1_dram.snoop_noneoffcore_response.pf_l1d_and_sw.l3_miss.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit.hitm_other_coreOCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit.snoop_missocr.all_data_rd.l3_hit_e.hit_other_core_no_fwdocr.all_data_rd.l3_hit_s.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_COREOCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDOCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_e.snoop_noneocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwdocr.all_pf_rfo.supplier_none.no_snoop_neededOCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONEOCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWDOCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_f.snoop_noneocr.all_reads.l3_hit_m.hitm_other_coreocr.all_reads.supplier_none.hit_other_core_fwdocr.all_rfo.any_responseocr.demand_code_rd.l3_hit_m.snoop_missocr.demand_data_rd.l3_hit.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOPocr.demand_rfo.l3_hit_e.hit_other_core_no_fwdocr.demand_rfo.l3_hit_m.any_snoopocr.demand_rfo.l3_hit_s.snoop_missCounts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.other.l3_hit.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDEDCounts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWDCounts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwdocr.pf_l1d_and_sw.l3_hit_s.snoop_noneCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_f.no_snoop_neededCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOPocr.pf_l2_rfo.l3_hit_f.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORECounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORECounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l3_rfo.supplier_none.snoop_noneAll Reads - RPQ or Ufillumask=0x08,event=0x2cCounts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementperiod=100003,umask=0x8,event=0xc7Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathperiod=1000003,umask=0x1,event=0x9cCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cacheocr.streaming_wr.any_responseocr.demand_data_rd.l3_hit.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1E003C8000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0184000001ocr.hwpf_l2_rfo.l3_hit.snoop_sentCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the requestCounts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector)br_misp_retired.indirectAll miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1Counts the number of lines that are evicted by the L2 cache due to L2 cache fills.  Evicted lines are delivered to the L3, which may or may not cache them, according to system load and prioritiesunc_m_tagchk.nm_rd_hitumask=0x02,event=0xeaunc_cha_tor_inserts.ia_miss_rfounc_cha_tor_inserts.ia_hit_drd_prefunc_cha_tor_inserts.ia_miss_drd_local_ddrfc_mask=0x04,umask=0x20,event=0xd5umask=0x08,event=0x11umask=0x02,event=0x2duncore_uboxTOR Inserts; DRd Opt misses from local IA. Unit: uncore_cha Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3period=200003,umask=0x8,event=0x34Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/Mperiod=1000003,umask=0x2,event=0x74Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stallsperiod=1000003,umask=0x8,event=0x71Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB missesperiod=200003,umask=0xfd,event=0xc4period=200003,umask=0x2,event=0x8Counts the number Extended Page Directory Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesL1 BTB Correctionic_cache_fill_sysumask=0x01,event=0x8cumask=0xf9,event=0x60l2_request_g2.bus_locks_responsesCore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2l2_cache_req_stat.ls_rd_blk_cumask=0xff,event=0x72All L3 Request Types. Unit: uncore_l3pmc event=0xc2Retired Branch Instructionsdram_channel_data_controller_1umask=0x38,event=0x107umask=0x40,event=0Total number multi-pipe uOps assigned to pipe 0The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipesThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Opsumask=0x80,event=0x3ls_l1_d_tlb_miss.tlb_reload_4k_l2_hitumask=0x02,event=0x52Cycles not in Haltl1_itlb_missesuops_retiredMicro-ops RetiredApproximate: Outbound data bytes for all Remote Links for a node (die)umask=0x04,event=0x94Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedL1 DTLB Miss. DTLB reload coalesced page missde_dis_dispatch_token_stalls1.load_queue_token_stallumask=0x08,event=0x85The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G pageSSE/AVX bottom-executing ops retired. The number of serializing Ops retiredThe number of retired CLFLUSH instructions. This is a non-speculative eventls_dmnd_fills_from_sys.lcl_l2Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 availableBU_CPU_CLK_UNHALTEDIC_REFILL_FROM_L2FR_DECODER_EMPTYCYCLES_NONIDLE_NEON_INTEVENT_00HEVENT_47HEVENT_5EHEVENT_84HEVENT_DBHEVENT_FCHLOAD_STORE_PIPEDSBSW_INCRCHAINLD_RETIREDL1D_CACHE_WB_VICTIMEXC_PABORTEXC_SMCEXC_TRAP_OTHERL3D_CACHEMEM_WORD_WRITEJTLB_IACCESSRF_CYCLES_STALLEDDC_BLOCKED_CYCLESCP2_STALL_CYCLESLDQ_FULL_PIPELINE_STALLSSINGLE_ISSUE_CYCLESDCACHE_LINE_REFILL_REQUESTSLDQ_FULL_STALLSSC_INSNSTWO_INSNS_CYCLESLDQ_LESS_25_FULLL1_INSTR_CACHE_MISSESLOAD_MISS_ALIAS_ON_TOUCHL1_DATA_STORE_HITLSU_CSQ_FORWARDINGSYNC_INSTR_COMPLETEDRUN_CYCLESGROUP_COMPLETEDPM_EVENT_CYCLESBRANCH_INSTRS_COMPLETEDCYCLES_LRU_SCHED_STALLEDLOAD_MISS_LDQ_FULL_CYCLESINTERRUPTS_TAKENL2_CACHE_DATA_HITSL2_CACHE_INSTR_ACCESSESFPU_INPUT_DATA_STALLSdirty-l2-victimscalar-sse-sse2sse-retype-microfaultsXSCALEOCTEONPPC970E500br_inst_retired.all_branchesUNC_uncoreGenuineIntel-6-3DGenuineIntel-6-4FGenuineIntel-6-26GenuineIntel-6-27GenuineIntel-6-85GenuineIntel-6-1EGenuineIntel-6-4CAuthenticAMD-23-[012][0-9A-F]C6 residency percent per coreC7 residency percent per coreoffcore_requests_outstanding.cycles_with_demand_rfooffcore_requests.demand_code_rdRetired load uops with L1 cache hits as data sources. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event)mem_load_uops_retired.hit_lfbThis event counts the number of L2 cache accesses when fetching instructionsl2_trans.all_pfThis event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejectsfp_assist.simd_inputidq.mite_cyclesCycles MITE is delivering any Uopidq.ms_cyclesumask=0x30,cmask=1,period=2000003,event=0x79Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FENumber of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts)Number of times RTM aborted and was not due to the abort conditions in subevents 3-6This event counts loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)ld_blocks_partial.address_aliasCycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the threadumask=0x10,period=2000003,event=0xeuops_issued.single_mulThis event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executedumask=0x2,period=100003,event=0x4cumask=0x41,period=200003,event=0x88Speculative and retired macro-unconditional branches excluding calls and indirectsThis event counts both taken and not taken speculative and retired indirect branches that have a return mnemonicuops_executed_port.port_2umask=0x10,period=2000003,event=0xa1umask=0x80,period=2000003,event=0xa1Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demandsumask=0xc,cmask=12,period=2000003,event=0xa3lsd.uopsThis event counts cycles during which no uops were dispatched from the Reservation Station (RS) per threaduops_retired.allThis is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)br_inst_retired.near_takenbr_misp_retired.near_takenLLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x4,event=0x1Conflict requests (requests for same address from multiple agents simultaneously). Unit: uncore_ha umask=0x8,event=0x21Counts the number of cycles when power is the upper limit on frequency. Unit: uncore_pcu unc_p_freq_trans_cyclesdtlb_store_misses.walk_completed_1gFlushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pagesThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPUIpBL2 cache true misses per kilo instruction for retired demand loadsoffcore_response.demand_data_rd.supplier_none.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0040umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0040Counts all prefetch (that bring data to LLC only) data readsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0080offcore_response.other.supplier_none.snoop_missoffcore_response.other.l3_hit.snoop_missoffcore_response.other.l3_hit.any_snoopumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020090Counts prefetch RFOs have any response typeumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0240offcore_response.all_rfo.supplier_none.snoop_hitmoffcore_response.all_rfo.l3_hit.any_snoopNumber of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)umask=0x10,period=2000003,cmask=1,event=0x79umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000004umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000008umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000020offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwdumask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000200umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084008000umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000090umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0120offcore_response.all_pf_rfo.l3_miss.snoop_not_neededoffcore_response.all_data_rd.l3_miss.snoop_noneumask=0x3,period=2000003,cmask=1,event=0xdinv=1,umask=0x1,period=2000003,cmask=1,event=0xb1unc_cbo_xsnp_response.hit_xcoreunc_cbo_cache_lookup.write_mesiUnit: uncore_arb Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent trafficumask=0x20,event=0x81( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * cycles )Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event)Counts prefetch (that bring data to LLC only) code reads hit in the L3Cycles the L2 transfers data to the corel2_ld.self.prefetch.mesiumask=0xa2,period=2000000,event=0x40umask=0x1,period=200000,event=0xcbsimd_uop_type_exec.unpack.arumask=0x90,period=2000000,event=0xb3CISC macro instructions decodeduops.ms_cyclesumask=0x97,period=200000,event=0x5Nonzero segbase store 1 bubblebus_data_rcv.selfbus_trans_mem.selfext_snoop.all_agents.anyAll store forwardsRetired branch instructionsBACLEARS assertedCounts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoopsumask=0x8,period=200003,event=0xd1umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000022Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredumask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000010Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitectureissue_slots_not_consumed.anyumask=0x4,period=200003,event=0xcbCounts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this eventAll machine clearsCounts machine clears for any reasonRetired far branch instructions (Precise event capable) (Must be precise)Counts near indirect call or near indirect jmp branch instructions retired (Must be precise)br_misp_retired.non_return_indCounts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor moduleoffcore_response.bus_locks.outstandingCounts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise)umask=0x21,period=100003,event=0xd0Retired load uops that split across a cacheline boundary. (precise Event)  Spec update: HSD29, HSM30.  Supports address when precise (Precise event)offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwdinput - Invalid Operation, Denormal Operand, SNaN Operand (Precise event)( uops_executed.core / 2 / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@) ) if #smt_on else uops_executed.core / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@)Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC08FFFoffcore_response.demand_rfo.l3_miss.local_draminv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xeild_stall.iq_fullCycles where at least 1 uop was executed per-thread  Spec update: HSD144, HSD30, HSM31Counts total number of uops to be executed per-core each cycle  Spec update: HSD30, HSM31An external snoop hits a modified line in some processor coreunc_cbo_xsnp_response.hitm_evictionDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load missesumask=0x81,period=2000003,event=0xbcumask=0x88,period=2000003,event=0xbcRetired load uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)umask=0x1,period=200003,event=0x24Requests from the L2 hardware prefetchers that miss L2 cacheCount the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)offcore_requests_outstanding.cycles_with_demand_code_rdOffcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncoreCases when offcore requests buffer cannot take more entries for coreRetired load uops whose data source was local memory (cross-socket snoop not needed or missed)Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0002dsb_fill.exceed_dsb_linesCounts demand data reads that miss the LLC and the data returned from dramunc_cbo_xsnp_response.hitunc_cbo_xsnp_response.eviction_filterUnit: uncore_arb Cycles weighted by number of requests pending in Coherency TrackerMisses in all ITLB levels that cause page walksCounts all prefetch data reads that hit the LLCoffcore_response.all_reads.llc_hit.no_snoop_neededCounts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedumask=0x3,event=0x35,filter_opc=0x19cumask=0x3,event=0x35,filter_opc=0x1e6PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read. Unit: uncore_cbox dtlb_load_misses.demand_ld_walk_durationThis event counts the number of store uops retired (Precise event)umask=0x1,period=100003,event=0xb6umask=0xf,period=2000003,event=0x5bCycles with either free list is emptyumask=0xf0,period=2000003,event=0xa2Counts the total number of L2 cache referencesumask=0x40,period=200003,event=0x4umask=0x80,period=200003,event=0x4Counts the matrix events specified by MSR_OFFCORE_RESPxumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400070umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400022Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.pf_l1_data_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000081000offcore_response.pf_software.l2_hit_near_tile_e_fCounts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateCounts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateCounts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_read.l2_hit_this_tile_moffcore_response.any_pf_l2.l2_hit_this_tile_mumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000070offcore_response.bus_locks.l2_hit_this_tile_sCounts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in S stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000044umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400004offcore_response.pf_l2_code_rd.l2_hit_far_tileoffcore_response.any_pf_l2.ddr_nearoffcore_response.bus_locks.mcdram_faroffcore_response.demand_rfo.ddr_faroffcore_response.demand_data_rd.mcdramCounts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far)offcore_response.pf_l1_data_rd.ddrCounts any request that accounts for responses from DDR (local and far)This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetchedumask=0x1,period=2000003,event=0xcdThis event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only onceumask=0x80,period=200003,event=0x3umask=0x01,event=0x1L1D cache lines replaced in M stateumask=0x4,period=2000000,event=0x42umask=0x1,period=2000000,event=0x52umask=0x2,period=2000000,event=0x41umask=0x1,period=200000,event=0xf0umask=0x8,period=200000,event=0xf0Retired loads that hit the L1 data cache (Precise Event)Memory instructions retired above 64 clocks (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x744Offcore writebacks to any cache or DRAMOffcore code or data read requests satisfied by any cache or DRAMoffcore_response.data_ifetch.llc_hit_other_core_hitOffcore code or data read requests satisfied by a remote cache or remote DRAMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x1077umask=0x1,period=100000,event=0xb7,offcore_rsp=0x233offcore_response.demand_data_rd.any_cache_dramoffcore_response.demand_data_rd.remote_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x780offcore_response.other.local_cache_dramoffcore_response.pf_data.local_cache_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF10offcore_response.pf_rfo.remote_cache_hitmfp_assist.allfp_comp_ops_exe.sse2_integerumask=0x8,period=2000000,event=0x10offcore_response.data_in.any_dramumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2002offcore_response.other.remote_dramoffcore_response.pf_data_rd.any_llc_missumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2020bpu_missed_call_retL1I instruction fetch missesrat_stalls.anyumask=0x4,period=2000000,event=0xd2umask=0x1,period=2000000,event=0xa7umask=0x8,period=2000,event=0x89lsd.inactiveinv=1,umask=0x1f,any=1,period=2000000,cmask=1,edge=1,event=0xb1inv=1,umask=0x1,period=2000000,cmask=16,event=0xc2umask=0x20,period=200000,event=0x8DTLB missesCounts L2 writebacks that access L2 cacheoffcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_neededCore-originated cacheable demand requests missed L3  Spec update: SKL057offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_neededperiod=200003,umask=0xc2,event=0x24Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion pointoffcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitmoffcore_response.demand_code_rd.supplier_none.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040088000offcore_response.demand_code_rd.l3_hit_s.snoop_not_neededfrontend_retired.itlb_missfrontend_retired.dsb_missCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)frontend_retired.latency_ge_64Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uopsperiod=100007,umask=0x1,event=0xc6,frontend=0x420006offcore_response.demand_rfo.l3_hit_s.snoop_non_dramoffcore_response.other.l3_miss.snoop_hitmperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x2000048000offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x203C400004offcore_response.demand_code_rd.l3_hit_m.snoop_non_dramperiod=2000003,umask=0x4,event=0xc9period=2000003,umask=0x8,event=0x32sw_prefetch_access.t1_t2period=2000003,umask=0x1,event=0x9arith.divider_activecmask=1,period=2000003,umask=0x1,event=0x14period=2000003,umask=0x1,event=0xa8cmask=1,edge=1,inv=1,period=2000003,umask=0x1,event=0x5eThis event counts both direct and indirect near call instructions retired  Spec update: SKL091 (Precise event)Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL productsperiod=2000003,umask=0x2,event=0xeAll (macro) branch instructions retired  Spec update: SKL091 (Must be precise)period=100007,umask=0x8,event=0xc4( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single ) / ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitectureLoads hit L2 (Precise event)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000044Counts any data read (demand & prefetch) that miss L2Counts any request that miss L2 with a snoop miss responseoffcore_response.pf_l1_data_rd.l2_miss.snoop_missCounts demand and DCU prefetch data read that miss L2 with a snoop miss responseIND_CALL counts the number of near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)D-side page-walksoffcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwdCounts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresumask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0120REQUEST = PF_RFO and RESPONSE = ANY_RESPONSENumber of any page walk that had a miss in LLC. Does not necessary cause a SUSPENDThis event counts any requests that miss the LLC where the data was returned from local DRAMumask=0x1,period=100003,event=0xb7,offcore_rsp=0x17004001b3This event counts the number of micro-ops retired. (Precise Event) (Precise event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5011umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7fffumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7ffoffcore_response.corewb.llc_hit_other_core_hitREQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITMREQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITMREQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff10REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISSumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3022REQUEST = CORE_WB and RESPONSE = REMOTE_DRAMREQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAMoffcore_response.pf_data_rd.other_local_dramREQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAMLoads that partially overlap an earlier storeumask=0x4,period=2000000,cmask=1,event=0xb3ITLB miss page walk cyclesumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2703umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F50umask=0x4,period=40000,event=0xfmem_load_l3_miss_retired.remote_drammem_load_l3_miss_retired.remote_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0122Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_pf_rfo.l3_miss.remote_hitmoffcore_response.all_rfo.l3_miss.remote_hit_forwardoffcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000020core_power.lvl0_turbo_licenseMemoryBound;MemoryLatL2_Evictions_NonSilent_PKIumask=0x21,event=0x35,config1=0x40041e33Snoop filter capacity evictions for M-state entries. Unit: uncore_cha Snoop filter capacity evictions for S-state entries. Unit: uncore_cha fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc0Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit. Unit: uncore_iio fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc1Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busCounts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part3Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Number of reads that a message sent direct2 Intel UPI was overridden. Unit: uncore_m2m unc_m2m_directory_update.s2aCounts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous readsCounts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller)BL Ingress (from CMS) Allocationsunc_upi_rxl_flits.all_nullFLITs that bypassed the TxL Buffer. Unit: uncore_upi ll This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.all_data_rd.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200490offcore_response.all_pf_data_rd.l3_hit_s.snoop_noneperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020490This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200120offcore_response.all_pf_rfo.supplier_none.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000807F7offcore_response.all_rfo.l3_hit_e.snoop_noneoffcore_response.demand_code_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_s.hitm_other_coreoffcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwdoffcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.demand_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080100offcore_response.pf_l3_rfo.l3_hit_e.snoop_noneoffcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwdoffcore_response.pf_l3_rfo.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONEocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreOCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISSocr.all_pf_data_rd.l3_miss_local_dram.snoop_missOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEOCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_COREocr.all_rfo.l3_miss.hit_other_core_no_fwdocr.demand_code_rd.l3_miss.remote_hit_forwardocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_data_rd.l3_miss_local_dram.snoop_noneCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C008000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C008000ocr.other.l3_miss_remote_hop1_dram.any_snoopCounts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_miss.snoop_missocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoopocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwdocr.pf_l2_data_rd.l3_miss.remote_hitmCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000020period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000080ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoopocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000100period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_missoffcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOPoffcore_response.demand_code_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISSoffcore_response.demand_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwdoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit.hit_other_core_no_fwdOCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_COREOCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDOCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONEOCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_pf_rfo.l3_hit_f.snoop_missocr.all_pf_rfo.l3_hit_s.any_snoopOCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_COREocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_neededOCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDEDOCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWDOCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_s.no_snoop_neededocr.all_reads.supplier_none.hitm_other_coreocr.all_reads.supplier_none.snoop_noneOCR.ALL_RFO.L3_HIT_F.SNOOP_MISSOCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORECounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_s.snoop_noneCounts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.demand_rfo.l3_hit_e.snoop_noneocr.demand_rfo.l3_hit_m.snoop_noneCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDCounts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWDCounts any other requests  OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORECounts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWDCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORECounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_m.snoop_noneocr.pf_l1d_and_sw.supplier_none.hitm_other_coreocr.pf_l2_data_rd.l3_hit_m.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOPocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwdocr.pf_l3_data_rd.l3_hit.snoop_noneocr.pf_l3_data_rd.l3_hit_f.snoop_noneocr.pf_l3_rfo.l3_hit.any_snoopCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORECounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_m.any_snoopocr.pf_l3_rfo.l3_hit_m.hitm_other_coreAll hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise (Precise event)cmask=1,period=1000003,umask=0x8,event=0x60l1d_pend_miss.l2_stallperiod=50021,umask=0x20,event=0xd1Cache lines that have been L2 hardware prefetched but not used by demand accessesCounts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementRetired Instructions who experienced DSB miss (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x510006period=100007,umask=0x1,event=0xc6,frontend=0x500206Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event)Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event)Counts the number of times RTM commit succeededCounts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.demand_code_rd.l3_hit.snoop_not_neededperiod=100003,umask=0x4,event=0x32Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the requestperiod=10000003,umask=0x2,event=0xa4period=500009,umask=0x1,event=0xdFar branch instructions retired (Precise event)Number of page walks outstanding for an outstanding code request in the PMH each cycleRetired load instructions which data source was serviced from L4  Supports address when precise (Precise event)umask=0xCCC7FD01,event=0x35umask=0xC817FE01,event=0x36TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha umask=0xC897FF01,event=0x35umask=0xC80FFF01,event=0x36umask=0xC896FE01,event=0x35unc_cha_tor_inserts.ia_miss_rfo_pref_remoteunc_cha_tor_inserts.io_itomcachenearunc_cha_tor_inserts.io_miss_itomcachenearTOR Inserts; WCiLF misses from local IA. Unit: uncore_cha umask=0xC8168601,event=0x35unc_cha_tor_occupancy.io_pcirdcurunc_iio_data_req_of_cpu.cmpd.part2unc_i_faf_transactionsumask=0x78,event=0x12Tag Hit : Dirty NearMem Read Hit. Unit: uncore_m2m umask=0x0720,event=0x37cycles_div_busy.anyumask=0xC001FE01,event=0x35,config1=0x40041e33umask=0xC001FE01,event=0x35,config1=0x41a33period=200003,umask=0x1,event=0x51mem_bound_stalls.ifetch_llc_hitCounts the number of load ops retired that hit in DRAM  Supports address when preciseCounts the number of load uops retired that miss in the L1 data cache  Supports address when precise (Precise event)This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCALocr.demand_data_and_l1pf_rd.any_responsetopdown_bad_speculation.machine_clearsCounts the number of page walks completed due to load DTLB misses to any page sizeept.epde_hitperiod=2000003,umask=0x8,event=0x4fperiod=200003,umask=0x11,event=0xd0The number of 32B fetch windows tried to read the L1 IC and missed in the full tagevent=0x99All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheableTotal cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be usedl2_cache_req_stat.ls_rd_blk_xumask=0x04,event=0x64SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)Total number multi-pipe uOps assigned to pipe 3umask=0x20,event=0fpu_pipe_assignment.dual0umask=0x08,event=0The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2umask=0x02,event=0fp_ret_sse_avx_ops.dp_add_sub_flopsNumber of Scalar Ops optimizedumask=0x02,event=0x4Counts the number of stores dispatched to the LS unit. Unit Masks ADDedls_l1_d_tlb_miss.tlb_reload_2m_l2_misstlbumask=0x04,event=0x85umask=0x01,event=0xaade_dis_dispatch_token_stalls1.int_phy_reg_file_token_stallThe number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size)Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cacheOp Cache Miss. Counts Op Cache micro-tag hit/miss eventsumask=0x7f,event=0x41Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Nodels_sw_pf_dc_fills.mem_io_remotels_sw_pf_dc_fills.mem_io_localde_dis_dispatch_token_stalls2.retire_token_stallde_dis_dispatch_token_stalls2.int_sch2_token_stallumask=0x48,event=0x44l1_data_cache_fills_from_external_ccx_cacheBU_FILL_REQUEST_L2_MISSPC_WRITEMEM_UNALIGNED_ACCESSPC_BRANCH_PREDEVENT_3DHEVENT_46HEVENT_5DHEVENT_B8HEVENT_E4HCOHERENT_LINEFILL_MISSCPLD_STALLL3D_CACHE_REFILLITLB_MISSDC_WRITEBACKJTLB_INSN_MISSESAGEN_EMPTY_CYCLESAGEN_OPERANDS_NOT_READY_CYCLESSTORE_INSTR_COMPLETEDFP_STORE_INSTR_COMPLETED_IN_LSUFPU_DENORMALIZATIONLSU_MISALIGNED_LOAD_FINISHVTQ_STREAM_CANCELED_PREMATURELYVTQ_RESUMES_DUE_TO_CTX_CHANGEBPU_STALL_ON_LR_DEPENDENCYPREFETCH_ENGINE_COLLISION_VS_LOADOVERFLOWFXU0_BUSY_FXU1_IDLELSU_COMPLETION_STALLGCT_EMPTY_BY_ICACHE_MISSCYCLES_WITH_INSTRS_COMPLETEDPM_EVENT_TRANSITIONSBTB_BRANCH_MISPRED_FROM_DIRECTIONCYCLES_BU_SCHED_STALLEDDATA_MMU_TLB4K_RELOADSL2_CACHE_CLEAN_REDUNDANT_UPDATESk8-fr-retired-x86-instructionsUCFINTEL_WESTMEREARMV7_CORTEX_A7umaskdata fabricGenuineIntel-6-4DUops Per InstructionPipelinemin( 1 , idq.mite_uops / ( uops_retired.retire_slots / inst_retired.any * 16 * ( icache.hit + icache.misses ) / 4.0 ) )CPISLOTSTurbo_Utilization(cstate_core@c6\-residency@ / msr@tsc@) * 100C3 residency percent per packageThis event counts the number of requests from the L2 hardware prefetchers that miss L2 cacheThis event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are countedOffcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request typeThis is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)L2 writebacks that access L2 cachel2_lines_in.alll2_lines_out.demand_cleanidq.emptyumask=0x8,period=2000003,event=0x79idq.dsb_cyclesThis event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEidq_uops_not_delivered.cycles_0_uops_deliv.coreCounts the number of times an instruction execution caused the transactional nest count supported to be exceededumask=0x2,period=100003,event=0xc3rtm_retired.startrtm_retired.aborted_misc3Loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3lock_cycles.split_lock_uc_lock_durationmove_elimination.int_eliminatedThis event counts both taken and not taken speculative and retired macro-conditional branch instructionsSpeculative and retired  branchesuops_executed_port.port_7umask=0x8,cmask=8,period=2000003,event=0xa3Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cacheuops_executed.stall_cyclesuops_executed.cycles_ge_1_uop_execNumber of uops executed on the coreCycles at least 1 micro-op is executed from any thread on physical coreCycles with no micro-ops executed from any thread on physical coreThis event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired (Precise event)unc_c_llc_victims.m_stateumask=0x3,event=0x35,filter_opc=0x190umask=0x3,event=0x35,filter_opc=0x1c8umask=0x3,event=0x1umask=0x4,event=0x21event=0xaCounts the number of cycles when the OS is the upper limit on frequency. Unit: uncore_pcu dtlb_load_misses.walk_completed_2m_4mdtlb_load_misses.walk_completedLoad operations that miss the first DTLB level but hit the second and do not cause page walksumask=0x2,period=100003,event=0x49itlb_misses.stlb_hit_2m1 / (inst_retired.any / cycles)TopDownL1_SMT( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )l1d_pend_miss.pending / l1d_pend_miss.pending_cyclesumask=0x4,period=2000003,cmask=1,event=0x60offcore_response.demand_code_rd.l3_hit.snoop_noneumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0004offcore_response.pf_l2_data_rd.supplier_none.snoop_missumask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0010umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0010offcore_response.pf_l2_rfo.supplier_none.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020020umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0080offcore_response.pf_l3_rfo.l3_hit.snoop_missoffcore_response.pf_l3_code_rd.supplier_none.snoop_hitmoffcore_response.other.l3_hit.snoop_not_neededumask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C8000Counts all prefetch data reads have any response typeoffcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwdCounts all prefetch code readsumask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0240offcore_response.all_data_rd.supplier_none.snoop_missCounts any FP_ASSIST umask was incrementing   (Precise Event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000001umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000004offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_neededoffcore_response.pf_l3_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000240umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000091offcore_response.all_rfo.l3_hit.snoop_non_dramumask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0122inv=1,umask=0x1,period=2000003,cmask=1,event=0xc2Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;Retired store uops that miss the STLB  Supports address when precise (Precise event)All retired store uops  Supports address when precise (Precise event)umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C07F7Number of times RTM abort was triggered  (Precise event)Counts all data/code/rfo reads (demand & prefetch) miss in the L3This event counts mispredicted conditional branch instructions retired (Precise event)Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data. Unit: uncore_qpi l2_lines_out.self.prefetchl2_ifetch.self.m_statel2_ld.self.prefetch.s_stateumask=0x58,period=200000,event=0x2eumask=0x1,period=2000000,event=0x10Floating point computational micro-ops retired (Must be precise)Floating point assists for retired operationsumask=0x0,period=2000000,event=0xb0simd_uop_type_exec.mul.arSIMD unpacked micro-ops retiredInstruction fetchesumask=0x1,period=2000000,event=0xaamisalign_mem_ref.ld_split.arLoad splits (At Retirement)umask=0x8c,period=200000,event=0x5umask=0xe0,period=200000,event=0x6cumask=0x40,period=200000,event=0x6cumask=0xe0,period=200000,event=0x6dext_snoop.all_agents.hitDivide operations retiredInstructions retiredumask=0x1,period=2000000,event=0xe4umask=0x2,period=2000000,event=0xcitlb.hitStores uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cacheumask=0x1,period=100007,event=0xb7,offcore_rsp=0x04000032b7offcore_response.any_rfo.l2_hitoffcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003010Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_hitoffcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwdoffcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_neededumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000008umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor moduleumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040004Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwdumask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000001References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitectureld_blocks.4k_aliasumask=0x10,period=2000003,event=0xc2Retired near relative call instructions (Precise event capable) (Must be precise)BACLEARs asserted for return branchCounts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetchmem_uops_retired.dtlb_miss_storesCounts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads (demand & prefetch) hit the L2 cacheCounts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132b7l2_lines_out.demand_dirtyNumber of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: HSD56, HSM57 (Precise event)umask=0x7,period=2000003,event=0xc6Number of times an RTM execution successfully committedNumber of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or notCycles which a uop is dispatched on port 3 in this threadThis events counts the cycles where at least one uop was executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31unc_cbo_cache_lookup.extsnp_mesiThis event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walksMisses at all ITLB levels that cause page walksNumber of DTLB page walker hits in the L2umask=0x48,period=2000003,event=0xbcoffcore_response.demand_data_rd.llc_miss.local_dramoffcore_response.pf_l2_data_rd.llc_miss.any_responseumask=0x1,period=100003,event=0xb7,offcore_rsp=0x06004007F7umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F8007F7l2_l1d_wb_rqsts.allAny MLC or LLC HW prefetch accessing L2, including rejectsumask=0x1,period=100003,event=0xf2umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0091Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedSample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise)uops_dispatched_port.port_2_coreCounts prefetch (that bring data to L2) data reads that hit in the LLCumask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400004offcore_response.demand_code_rd.llc_miss.remote_hit_forwardCounts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cacheMemory page activates for reads and writes. Unit: uncore_imc event=0xc,edge=1,filter_band1=20offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forwardumask=0x40,period=2000003,event=0x5bCycles when Allocator is stalled if BOB is full and new branch needs itCycles per core when load or STA uops are dispatched to port 2Resource stalls due to load or store buffers all being in useNumber of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)umask=0x2,period=100003,event=0x8umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400070offcore_response.uc_code_reads.l2_hit_far_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000040offcore_response.demand_code_rd.l2_hit_near_tile_e_fumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400002offcore_response.demand_rfo.l2_hit_near_tile_mCounts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M stateCounts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_pf_l2.l2_hit_this_tile_eCounts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in S stateCounts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F stateumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000022umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180100Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateCounts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeCounts Demand cacheable data write requests  that accounts for data responses from DRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100408000Counts any request that accounts for data responses from MCDRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100402000offcore_response.bus_locks.ddr_farCounts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Localumask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020080Counts L2 code HW prefetches that accounts for data responses from DRAM Faroffcore_response.demand_rfo.ddr_nearumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800002Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM LocalCounts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)offcore_response.any_request.mcdramumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181803091Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far)Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store  Supports address when precise (Precise event)recycleq.ld_splitsCounts any retired load that was pushed into the recycle queue for any reasonumask=0x1,period=2000000,event=0x51umask=0xf,period=2000000,event=0x40umask=0x4,period=200000,event=0x26L2 lines evicted by a prefetch requestL2 prefetch missesumask=0x40,period=100000,event=0x27l2_write.lock.mesiAll demand L2 lock RFOsl2_write.lock.s_stateumask=0x2,period=100000,event=0x27Retired loads that miss the LLC cache (Precise Event)Retired loads that hit valid versions in the LLC cache (Precise Event)umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1044offcore_response.any_request.remote_cacheoffcore_response.any_rfo.llc_hit_no_other_coreoffcore_response.data_in.remote_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF01umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1801offcore_response.demand_rfo.remote_cache_hitmOffcore demand RFO requests that HITM in a remote cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x430offcore_response.pf_data.local_cacheumask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F10offcore_response.pf_data_rd.llc_hit_no_other_coreumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3810Offcore prefetch code reads that HITM in a remote cachefp_comp_ops_exe.sse_fpumask=0x10,period=2000000,event=0x10umask=0x3,period=2000000,event=0xccumask=0x10,period=200000,event=0x12umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6011Offcore RFO requests satisfied by the local DRAMoffcore_response.prefetch.remote_dramumask=0x1,period=2000000,event=0xe8ES segment renamessnoop_response.hitinv=1,umask=0x1,period=2000000,cmask=1,edge=1,event=0x14baclear.clearumask=0x2,period=200000,event=0x88Mispredicted non call branches executedumask=0x8,period=2000000,event=0xa2SIMD Vector Integer Uops retired (Precise Event)umask=0x1,period=2000000,event=0xdbCycles Uops executed on any port (core count)Uops issued on ports 0, 1 or 5Uops issuedumask=0x1,period=200000,event=0x8DTLB load miss page walks completeRetired instructions that missed the ITLB (Precise Event)Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded eventperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080001period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020001Counts L2 cache misses when fetching instructionsperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400088000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200088000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200048000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100002period=200003,umask=0xe1,event=0x24period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040408000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0040400002period=100003,umask=0x80,event=0xb0mem_load_retired.l1_hitCounts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entriesRetired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_1Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQperiod=100007,umask=0x1,event=0xc6,frontend=0x12offcore_response.demand_rfo.l3_hit_e.snoop_non_dramCounts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise (Must be precise)period=2000003,umask=0x2,event=0xc9offcore_response.demand_rfo.l3_miss.spl_hitperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FC4008000offcore_response.demand_code_rd.l3_hit_s.snoop_non_dramCounts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliasedperiod=2000003,umask=0x8,event=0xa1Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector)period=2000003,umask=0x1,event=0x59period=2000003,umask=0x1,event=0xeperiod=400009,umask=0x1,event=0xc4period=400009,event=0xc4All (macro) branch instructions retired  Spec update: SKL091skl metricsBpTkBranchEach cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficCounts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitectureCounts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultThis event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right timeThis event counts the number of load ops retired that hit in the L2 (Precise event)mem_uops_retired.utlb_missoffcore_response.any_rfo.l2_miss.snoop_missumask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000040FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise)Total cycles for all the page walks. (I-side and D-side)Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event)Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwdumask=0x4,period=2000000,cmask=1,event=0x60offcore_response.any_data.all_local_dram_and_remote_cache_hitREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITMumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2ffoffcore_response.any_rfo.all_local_dram_and_remote_cache_hitREQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIToffcore_response.any_rfo.local_dram_and_remote_cache_hitoffcore_response.corewb.all_local_dram_and_remote_cache_hitumask=0x1,period=100000,event=0xb7,offcore_rsp=0xff77REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAMREQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIToffcore_response.data_in.other_local_dramREQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAMREQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISSREQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWDumask=0x1,period=100000,event=0xb7,offcore_rsp=0x3020DTLB load miss page walk cyclesumask=0x20,period=100000,event=0xb0umask=0x1,period=100000,event=0xb7,offcore_rsp=0x58FFumask=0x1,period=100000,event=0xb7,offcore_rsp=0x2777umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2770mem_uncore_retired.local_hitmLoad instructions retired local dram and remote cache HIT data sources (Precise Event)Cycles thread is activeCounts prefetch RFOs that have any response typeOFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDCounts all demand code reads that have any response typeOFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWDCounts demand data reads that have any response typeCounts all prefetch (that bring data to LLC only) data reads that hit in the L3period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0100Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementoffcore_response.all_pf_data_rd.l3_miss.any_snoopCounts prefetch RFOs that miss in the L3Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000010DSB;FetchBWHPC;MemoryBW;SoCumask=0x03,event=0x50unc_cha_requests.writes_localunc_iio_data_req_of_cpu.mem_read.part3unc_cha_requests.invitoe_remoteCounts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  statesunc_iio_data_req_by_cpu.mem_read.part0unc_iio_data_req_of_cpu.peer_read.part0unc_iio_txn_req_by_cpu.mem_read.part1fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc1Read request for up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x84umask=0x10,event=0x10unc_m2m_direct2upi_not_taken_creditsumask=0x1,event=0x2dCounts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socketumask=0x40,event=0x2eCounts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared)AD Egress (to CMS) AllocationsAD Egress (to CMS) Occupancyumask=0x1,event=0x12Null FLITs received from any slot. Unit: uncore_upi ll unc_upi_txl_bypassedumask=0x47,event=0x2Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event  Supports address when precise (Precise event)This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200491offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwdoffcore_response.all_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONEperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200120period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISSoffcore_response.all_reads.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200002This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_e.hit_other_core_fwdperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80108000period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0400offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400400period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020400offcore_response.pf_l2_data_rd.l3_hit_f.any_snoopperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200010period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOPperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100010offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_coreperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100020offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_neededoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDLSD( ( 64 * imc@event\=0xe7@ / 1000000000 ) / duration_time )period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000491period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEOCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss.remote_hit_forwardOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss_local_dram.no_snoop_neededOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_missperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC0007F7period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04100007F7OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITMOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000004period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000004ocr.demand_data_rd.l3_miss.any_snoopocr.demand_data_rd.l3_miss.no_snoop_neededperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000001ocr.demand_rfo.l3_miss_local_dram.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWDperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000400Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOPCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000080This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_coreoffcore_response.all_rfo.l3_miss.hitm_other_coreoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_missoffcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_noneoffcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_f.no_snoop_neededocr.all_data_rd.l3_hit_s.any_snoopOCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREOCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response typeocr.all_pf_data_rd.l3_hit.snoop_missocr.all_pf_data_rd.l3_hit_e.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_m.snoop_missOCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_COREOCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_pf_data_rd.supplier_none.snoop_noneocr.all_pf_rfo.l3_hit_f.any_snoopocr.all_pf_rfo.l3_hit_m.hitm_other_coreOCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.pmm_hit_local_pmm.snoop_noneOCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOPocr.all_reads.l3_hit_m.snoop_noneOCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_COREOCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONEocr.all_rfo.l3_hit_e.no_snoop_neededocr.all_rfo.l3_hit_m.hitm_other_coreocr.all_rfo.l3_hit_s.no_snoop_neededOCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOPOCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORECounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDEDCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_s.hitm_other_coreocr.demand_data_rd.l3_hit_m.snoop_noneocr.demand_data_rd.pmm_hit_local_pmm.any_snoopCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.demand_data_rd.supplier_none.snoop_missocr.demand_rfo.l3_hit_e.snoop_missCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_m.no_snoop_neededocr.demand_rfo.l3_hit_m.snoop_missCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.pf_l2_data_rd.l3_hit_s.any_snoopocr.pf_l2_data_rd.supplier_none.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDEDCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORECounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOPocr.pf_l3_data_rd.l3_hit_e.any_snoopCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOPCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.pf_l3_data_rd.supplier_none.hitm_other_coreocr.pf_l3_rfo.l3_hit.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED6.103515625E-5MB/secunc_m2m_imc_writes.to_pmmunc_m2m_tag_hit.nm_rd_hit_dirtyTag Hit; Underfill Rd Hit from NearMem, Dirty  LineCounts all microcode Floating Point assistsidq.dsb_cycles_anyCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accessesCounts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)period=100007,umask=0x1,event=0xc6,frontend=0x500406idq.dsb_cycles_okCounts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleCounts demand data reads that was not supplied by the L3 cacheperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FFFC00010period=100003,umask=0x8,event=0xc8cmask=1,period=1000003,umask=0x10,event=0x60Number of machine clears due to memory ordering conflictsocr.other.l3_missocr.hwpf_l2_rfo.dramperiod=100003,umask=0x1,event=0xb7,offcore_rsp=0x1E003C0001ocr.hwpf_l2_data_rd.l3_hit.snoop_sentocr.demand_rfo.local_dramperiod=100003,umask=0x80,event=0xc4uops_dispatched.port_5Mispredicted non-taken conditional branch instructions retired (Precise event)Taken conditional branch instructions retired (Precise event)mem_load_l3_hit_retired.xsnp_no_fwdevent=0x82unc_m_wpq_occupancy_pch1umask=0x0F,event=0x37umask=0xC001FD01,event=0x35umask=0xC80FFD01,event=0x35TOR Inserts : DRd_Prefs issued by iA Cores. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha umask=0xC806FE01,event=0x35TOR Inserts : LLCPrefData issued by iA Cores. Unit: uncore_cha fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0xc0fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0xc0unc_iio_txn_req_by_cpu.mem_write.part4Number of kfclks. Unit: uncore_upi ll Counts the number of load uops retired  Supports address when precise (Precise event)Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICacheClockticks of the power control unit (PCU)Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetchesCounts the number of BACLEARS due to an indirect branchperiod=200003,umask=0x8,event=0xe6Counts the number of BACLEARS due to a non-indirect, non-conditional jumpCounts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same linebus_lock.cycles_self_blockc0_stalls.load_l2_hittopdown_be_bound.registerCounts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls)period=1000003,umask=0x40,event=0x71Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARSperiod=200003,umask=0x1,event=0xcdCounts the number of page walks due to loads that miss the PDE (Page Directory Entry) cacheCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page faultCounts the number of page walks completed due to store DTLB misses to a 2M or 4M pageCounts the number of page walks completed due to instruction fetch misses to a 4K pageumask=0x01,event=0x87All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch)umask=0x01,event=0x61Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2l2_cache_req_stat.ls_rd_blk_l_hit_sumask=0x08,event=0x64umask=0xfe,event=0x6ex_ret_copsex_ret_near_retx87 instructionsremote_outbound_data_controller_2Total number multi-pipe uOps assigned to pipe 1umask=0x08,event=0x4umask=0x02,event=0x41Software Prefetch Instructions (PREFETCHNTA instruction) Dispatchedumask=0x02,event=0x4bAll L2 Cache Hitsl2_cache_hits_from_dc_missesAverage L3 Read Miss Latency (in core clocks)umask=0x07,event=0x85all_tlbs_flushedLS MAB Allocates by Type. Storesls_refills_from_sys.ls_mabresp_lcl_dramAll L1 DTLB Misses or ReloadsSoftware Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevells_sw_pf_dc_fill.ls_mabresp_lcl_cacheumask=0x40,event=0xaeAny Data Cache Fills by Data Source. From DRAM or IO connected in different Nodeop_cache_fetch_miss_ratioL1 Data Cache Fills: From Remote Nodel1_data_cache_fills_from_within_same_ccx��A���!��������h���
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